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AT91SAM9260_08 PDF预览

AT91SAM9260_08

更新时间: 2024-02-26 03:12:16
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
47页 1622K
描述
AT91 ARM Thumb Microcontrollers

AT91SAM9260_08 数据手册

 浏览型号AT91SAM9260_08的Datasheet PDF文件第2页浏览型号AT91SAM9260_08的Datasheet PDF文件第3页浏览型号AT91SAM9260_08的Datasheet PDF文件第4页浏览型号AT91SAM9260_08的Datasheet PDF文件第5页浏览型号AT91SAM9260_08的Datasheet PDF文件第6页浏览型号AT91SAM9260_08的Datasheet PDF文件第7页 
Features  
Incorporates the ARM926EJ-SARM® Thumb® Processor  
– DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration  
– 8-KByte Data Cache, 8-KByte Instruction Cache, Write Buffer  
– 200 MIPS at 180 MHz  
– Memory Management Unit  
– EmbeddedICE, Debug Communication Channel Support  
Additional Embedded Memories  
– One 32 KByte Internal ROM, Single-cycle Access At Maximum Matrix Speed  
– Two 4 KByte Internal SRAM, Single-cycle Access At Maximum Matrix Speed  
External Bus Interface (EBI)  
– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash®  
USB 2.0 Full Speed (12 Mbits per second) Device Port  
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM  
USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-lead PQFP  
Package and Double Port in 217-ball LFBGA Package  
– Single or Dual On-chip Transceivers  
AT91 ARM  
Thumb  
Microcontrollers  
AT91SAM9260  
Summary  
– Integrated FIFOs and Dedicated DMA Channels  
Ethernet MAC 10/100 Base T  
– Media Independent Interface or Reduced Media Independent Interface  
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit  
Image Sensor Interface  
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate  
– 12-bit Data Interface for Support of High Sensibility Sensors  
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format  
Bus Matrix  
– Six 32-bit-layer Matrix  
– Boot Mode Select Option, Remap Command  
Fully-featured System Controller, including  
– Reset Controller, Shutdown Controller  
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes  
– Clock Generator and Power Management Controller  
– Advanced Interrupt Controller and Debug Unit  
– Periodic Interval Timer, Watchdog Timer and Real-time Timer  
Reset Controller (RSTC)  
– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output  
Control  
Clock Generator (CKGR)  
– Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on  
Battery Backup Power Supply, Providing a Permanent Slow Clock  
– 3 to 20 MHz On-chip Oscillator, One up to 240 MHz PLL and One up to 130 MHz PLL  
Power Management Controller (PMC)  
– Very Slow Clock Operating Mode, Software Programmable Power Optimization  
Capabilities  
– Two Programmable External Clock Signals  
Advanced Interrupt Controller (AIC)  
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources  
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious  
Interrupt Protected  
6221IS–ATARM–12-Aug-08  

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