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AT83C5112 PDF预览

AT83C5112

更新时间: 2024-02-28 20:02:53
品牌 Logo 应用领域
爱特美尔 - ATMEL 转换器微控制器
页数 文件大小 规格书
97页 1160K
描述
8-bit Microcontroller with A/D Converter

AT83C5112 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP,
针数:48Reach Compliance Code:unknown
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.92具有ADC:YES
其他特性:OPERATES AT 2.7V MINIMUM SUPPLY @ 40 MHZ地址总线宽度:
位大小:8最大时钟频率:40 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:S-PQFP-G48
长度:7 mm湿度敏感等级:1
I/O 线路数量:37端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):225
认证状态:Not QualifiedROM可编程性:MROM
座面最大高度:1.6 mm速度:40 MHz
最大供电电压:5.5 V最小供电电压:2.7 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

AT83C5112 数据手册

 浏览型号AT83C5112的Datasheet PDF文件第4页浏览型号AT83C5112的Datasheet PDF文件第5页浏览型号AT83C5112的Datasheet PDF文件第6页浏览型号AT83C5112的Datasheet PDF文件第8页浏览型号AT83C5112的Datasheet PDF文件第9页浏览型号AT83C5112的Datasheet PDF文件第10页 
AT8xC5112  
Table 2. Pin Description (Continued)  
PIN NUMBER  
TYPE  
LQFP PLCC  
Mnemonic  
48  
52  
Name and Function  
AIN4 (P4.4): A/D converter input 4  
I/O  
I/O  
I/O  
MISO: Master IN, Slave OUT of the SPI controller  
AIN5 (P4.5): A/D converter input 5  
MOSI: Master OUT, Slave IN of the SPI controller  
AIN6 (P4.6): A/D converter input 6  
SPSCK: Clock I/O of the SPI controller  
I/O  
I/O  
AIN7 (P4.7): A/D converter input 7  
P0.0-P0.7  
P2.0-P2.7  
X
X
X
X
Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s written to them float and can be  
used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during access to  
external program and data memory. In this application, it uses strong internal pull-up when emitting 1s.  
I/O  
Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1s written to them  
are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally  
pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during  
fetches from external program memory and during accesses to external data memory that use 16-bit  
addresses (MOVX atDPTR). In this application, it uses strong internal pull-ups emitting 1s. During accesses to  
external data memory that use 8-bit addresses (MOVX atRi), port 2 emits the contents of the P2 SFR.  
RST  
ALE  
X
X
X
X
I
RST: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal  
diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. If the hardware  
watchdog reaches its time-out, the reset pin becomes an output during the time the internal reset is activated.  
O
Address Latch Enable: Output pulse for latching the low byte of the address during an access to external  
memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,  
and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to  
external data memory. ALE can be disabled by setting SFRs AUXR.0 bit. With this bit set, ALE will be inactive  
during internal fetches.  
PSEN  
EA  
X
X
X
X
O
I
Program Store Enable: The read strobe to external program memory. When executing code from the external  
program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped  
during each access to external data memory. PSEN is not activated during fetches from internal program  
memory.  
External Access Enable: EA must be externally held low to enable the device to fetch code from external  
program memory locations 0000H and 1FFFH . If EA is held high, the device executes from internal program  
memory unless the program counter contains an address greater than 1FFFH. EA must be held low for  
ROMless devices. If security level 1 is programmed, EA will be internally latched on Reset.  
XTAL1  
XTAL2  
X
X
I
XTAL1 : Input to the inverting oscillator amplifier and input to the internal clock generator circuits.  
XTAL2 : Output from the inverting oscillator amplifier.  
O
7
4191B805104/03  

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