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AT83C5103XXX-ICSIL PDF预览

AT83C5103XXX-ICSIL

更新时间: 2024-02-19 01:36:41
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器和处理器外围集成电路光电二极管异步传输模式ATM时钟
页数 文件大小 规格书
64页 684K
描述
Low-pin Count 8-bit Microcontroller

AT83C5103XXX-ICSIL 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP24,.3
针数:24Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.49
Is Samacsys:N具有ADC:NO
地址总线宽度:位大小:8
CPU系列:8051最大时钟频率:16 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:8.2 mm
湿度敏感等级:1I/O 线路数量:19
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP24,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:3/5 V认证状态:Not Qualified
RAM(字节):512ROM(单词):12288
ROM可编程性:MROM座面最大高度:1.99 mm
速度:16 MHz子类别:Microcontrollers
最大压摆率:25 mA最大供电电压:5.5 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:5.29 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

AT83C5103XXX-ICSIL 数据手册

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AT8xC5103  
Clock  
The Errata Sheet core needs only 6 clock periods per machine cycle. This feature,  
called ”X2”, provides the following advantages:  
Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU  
power.  
Saves power consumption while keeping the same CPU power (oscillator power  
saving).  
Saves power consumption by dividing dynamic operating frequency by 2 in  
operating and idle modes.  
Increases CPU power by 2 while keeping the same crystal frequency.  
In order to keep the original C51 compatibility, a divider-by-2 is inserted between the  
XTAL1 signal and the main clock input of the core (phase generator). This divider may  
be disabled by the software.  
Description  
The clock for the whole circuit and peripheral is first divided by 2 before being used by  
the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1  
input. In X2 Mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic  
ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. The X2  
bit is validated on the XTAL1 ÷ 2 rising edge to avoid glitches when switching from the  
X2 to the STD mode. Figure 2 shows the mode switching waveforms.  
5
4134C–8051–09/04  

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