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AT83C5103XXX-IBSIL PDF预览

AT83C5103XXX-IBSIL

更新时间： 2024-01-24 21:28:27
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
64页 684K
描述
Low-pin Count 8-bit Microcontroller

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AT83C5103XXX-IBSIL 数据手册

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AT8xC5103  
Clock  
The Errata Sheet core needs only 6 clock periods per machine cycle. This feature,  
called ”X2”, provides the following advantages:  
•
•
•
•
Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU  
power.  
Saves power consumption while keeping the same CPU power (oscillator power  
saving).  
Saves power consumption by dividing dynamic operating frequency by 2 in  
operating and idle modes.  
Increases CPU power by 2 while keeping the same crystal frequency.  
In order to keep the original C51 compatibility, a divider-by-2 is inserted between the  
XTAL1 signal and the main clock input of the core (phase generator). This divider may  
be disabled by the software.  
Description  
The clock for the whole circuit and peripheral is first divided by 2 before being used by  
the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1  
input. In X2 Mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic  
ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. The X2  
bit is validated on the XTAL1 ÷ 2 rising edge to avoid glitches when switching from the  
X2 to the STD mode. Figure 2 shows the mode switching waveforms.  
5
4134C–8051–09/04  
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