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AT40K10LV-3BQI

更新时间： 2024-02-27 06:01:53

品牌	Logo	应用领域
爱特美尔 - ATMEL		现场可编程门阵列可编程逻辑栅异步传输模式 ATM
页数	文件大小	规格书
67页	1491K
描述
5K - 50K Gates Coprocessor FPGA with FreeRAM

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AT40K10LV-3BQI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	QFP,
针数：	100	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.9
Is Samacsys：	N	其他特性：	MAXIMUM USABLE GATES 20000
CLB-Max的组合延迟：	3.4 ns	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
湿度敏感等级：	1	可配置逻辑块数量：	576
等效关口数量：	10000	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	576 CLBS, 10000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	225
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	3.4 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

AT40K10LV-3BQI 数据手册

The Busing Network

Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus

resources: a local-bus resource (the middle bus) and two express-bus (both sides)

resources. Bus resources are connected via repeaters. Each repeater has connections

to two adjacent local-bus segments and two express-bus segments. Each local-bus

segment spans four cells and connects to consecutive repeaters. Each express-bus

segment spans eight cells and “leapfrogs” or bypasses a repeater. Repeaters regener-

ate signals and can connect any bus to any other bus (all pathways are legal) on the

same plane. Although not shown, a local bus can bypass a repeater via a programma-

ble pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are

implemented through pass gates in the cell-bus interface. Express/Express turns are

implemented through separate pass gates distributed throughout the array.

Some of the bus resources on the AT40K/AT40KLV are used as a dual-function

resources. Table 2 shows which buses are used in a dual-function mode and which bus

plane is used. The AT40K/AT40KLV software tools are designed to accommodate dual-

function buses in an efficient manner.

Table 2. Dual-function Buses

Function

Type

Plane(s) Direction

Comments

Cell Output Enable

Local

Horizontal

and Vertical

RAM Output Enable Express

Vertical

Bus full length at array edge

Bus in first column to left of

RAM block

RAM Write Enable

RAM Address

Express

Bus full length at array edge

Bus in first column to left of

RAM block

1 - 5

Buses full length at array edge

Buses in second column to left

of RAM block

RAM Data In

Local

Horizontal

Data In connects to local

bus plane 1

RAM Data Out

Data out connects to local

bus plane 2

Clocking

Express

Vertical

Bus half length at array edge

Set/Reset

AT40K/AT40KLV Series FPGA

0896C–FPGA–04/02

1...3 4 567 8 9...67

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与AT40K10LV-3BQI相关器件

型号	品牌	描述	获取价格	数据表
AT40K10LV-3CQC	ATMEL	5K - 50K Gates Coprocessor FPGA with FreeRAM	获取价格
AT40K10LV-3CQI	ATMEL	5K - 50K Gates Coprocessor FPGA with FreeRAM	获取价格
AT40K10LV-3DQC	ATMEL	5K - 50K Gates Coprocessor FPGA with FreeRAM	获取价格
AT40K10LV-3DQI	ATMEL	5K - 50K Gates Coprocessor FPGA with FreeRAM	获取价格
AT40K10LV-3EQC	ATMEL	Field Programmable Gate Array, 576 CLBs, 10000 Gates, 576-Cell, CMOS, PQFP240, PLASTIC, QF	获取价格
AT40K10LV-3RQC	ATMEL	5K - 50K Gates Coprocessor FPGA with FreeRAM	获取价格

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