Datasheet > AT22V10L-30GM/883

AT22V10L-30GM/883

更新时间： 2024-02-14 19:08:50

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟输入元件可编程逻辑
页数	文件大小	规格书
11页	188K
描述
Programmable Logic Device

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AT22V10L-30GM/883 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.82

AT22V10L-30GM/883 数据手册

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Preload of Registered Outputs

The registers in the AT22V10 and AT22V10L are provided

with circuitry to allow loading of each register asynchro-

nously with either a high or a low. This feature will simplify

testing since any state can be forced into the registers to con-

trol test sequencing. A V_IHlevel on the I/O pin will force the

bit (C0) setting. The preload state is entered by placing an

11.5-V to

Level forced on

registered output pin

during preload cycle

after cycle

High

Low

13-V signal on pin 8 on DIPs, and pin 10 on SMPs. When the

clock pin is pulsed high, the data on the I/O pins is placed into

the ten registers.

t_DMIN= 100 ns

PRELOAD

CLOCK

REGISTERED

OUTPUTS

OUTPUT

PRELOADENA. FORCEI/O’S PRELOADDATA

OUTPUTSDIS. TO VIH ORVIL CLOCKEDIN

VOLTAGE

REMOVED

PRELOAD

DISABLED

Power Up Reset

3.8 V

The registers in the AT22V10 and AT22V10L are designed to

reset during power up. At a point delayed slightly from V_CC

crossing 3.8 V, all registers will be reset to the low state. The

output state will depend on the polarity of the output buffer.

POWER

tPR

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the uncer-

tainty of how V_CCactually rises in the system, the following

conditions are required:

REGISTERED

OUTPUTS

1) The V_CCrise must be monotonic,

CLOCK

2) After reset occurs, all input and feedback setup times

must be met before driving the clock pin high, and

3) The clock must remain stable during t_PR

Description

Parameter

Min Typ Max Units

Power-Up

Reset Time

600 1000

Pin Capacitance (f = 1 MHz, T = 25°C) ⁽¹⁾

Typ

Max

Units

Conditions

= 0 V

OUT

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

Erasure Characteristics

The entire fuse array of an AT22V10 or AT22V10L is erased

after exposure to ultraviolet light at a wavelength of 2537 Å.

Complete erasure is assured after a minimum of 20 minutes

exposure using 12,000 µW/cm²intensity lamps spaced one

inch away from the chip. Minimum erase time for lamps at

other intensity ratings can be calculated from the minimum

integrated erasure dose of 15 W^•sec/cm². To prevent unin-

tentional erasure, an opaque label is recommended to cover

the clear window on any UV erasable PLD which will be sub-

jected to continuous fluorescent indoor lighting or sunlight.

1-102

AT22V10/L

1...3 4 567 8 9...11

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