80C154/83C154
The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.0 can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
PCON : Power Control Register
(MSB)
(LSB)
IDL
SMOD HPD
RPD
–
GF1
GF0
PD
Symbol
Position
Name and Function
SMOD
PCON.7
Double Baud rate bit. When set to
a 1, the baud rate is doubled when
the serial port is being used in
either modes 1, 2 or 3.
Hard power Down bit. Setting this
bit allows CPU to enter in Power
Down state on an external event
(1 to 0 transition) on bit T1
(p. 3.5) the CPU quit the Hard
Power Down mode when bit T1
p. 3.5) goes high or when reset is
activated.
Recover from Idle or Power Down
bit. When 0 RPD has no effetc.
When 1, RPD permits to exit from
idle or Power Down with any non
enabled interrupt source (except
time 2). In this case the program
start at the next address. When
interrupt is enabled, the
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
HPD
RPD
PCON.6
PCON.5
The third way to terminate the Idle mode is the activation
of any disabled interrupt when recover is programmed
(RPD = 1). This will cause PCON.0 to be cleared. No
interrupt is serviced. The next instruction is executed. If
interrupt are disabled and RPD = 0, only a reset can
cancel the Idle mode.
Power Down Mode
The instruction that sets PCON.1 is the last executed prior
to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM and
the Special Function Register is saved during power down
mode. The three ways to terminate the Power Down mode
are the same than the Idle mode. But since the onchip
oscillator is stopped, the external interrupts, timers and
serial port must be sourced by external clocks only, via
INT0, INT1, T0, T1.
appropriate interrupt routine is
serviced.
General-purpose flag bit.
GF1
GF0
PD
PCON.3
PCON.2
PCON.1
General-purpose flag bit.
Power Down bit. Setting this bit
activates power down operation.
Idle mode bit. Setting this bit
activates idle mode operation.
IDL
PCON.0
If 1’s are written to PD and IDL at the same time. PD
takes, precedence. The reset value of PCON is
(000X0000).
In the Power Down mode, VCC may be lowered to
minimize circuit power consumption. Care must be taken
to ensure the voltage is not reduced until the power down
mode is entered, and that the voltage is restored before the
hardware reset is applied which frees the oscillator. Reset
should not be released until the oscillator has restarted
and stabilized.
Idle Mode
The instruction that sets PCON.0 is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety : the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM and all other registers maintain their
data during idle. In the idle mode, the internal clock signal
is gated off to the CPU, but interrupt, timer and serial port
functions are maintained. Table 1 describes the status of
the external pins during Idle mode. There are three ways
to terminate the Idle mode. Activation of any enabled
interrupt will cause PCON.0 to be cleared by hardware,
terminating Idle mode. The interrupt is serviced, and
following RETI, the next instruction to be executed will
be the one following the instruction that wrote 1 to
PCON.0.
When using voltage reduction : interrupt, timers and
serial port functions are guaranteed in the VCC
specification limits.
Table 1 describes the status of the external pins while in
the power down mode. It should be noted that if the power
down mode is activated while in external program
memory, the port data that is held in the Special Function
Register P2 is restored to Port 2. If the port switches from
0 to 1, the port pin is held high during the power down
mode by the strong pullup, T1, shown in figure 4.
6
MATRA MHS
Rev.F (14 Jan. 97)
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