Datasheet > AS4LC1M16EC-7

AS4LC1M16EC-7

更新时间： 2024-02-25 02:32:49

品牌	Logo	应用领域
MICROSS		动态存储器
页数	文件大小	规格书
22页	195K
描述
DRAM

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AS4LC1M16EC-7 数据手册

AS4LC1M16 883C

1 MEG x 16 DRAM

AUSTIN SEMICONDUCTOR, INC.

PRELIMINARY

EDO PAGE MODE (continued)

WE can also perform the function of disabling the output

drivers under certain conditions, as shown in Figure 2.

During an application, if the DQ outputs are wire OR’d,

OE must be used to disable idle banks of DRAMs. Alterna-

tively, pulsing WEto the idle banks during CASHIGH time

will also High-Z the outputs. Independent of OE control,

the outputs will disable after OFF, which is referenced

from the rising edge of RAS or CAS, whichever occurs last.

RAS

CASL/CASH

ADDR

ROW

COLUMN (A)

COLUMN (B)

COLUMN (C)

COLUMN (D)

IOH

IOL

OPEN

VALID DATA (A)

VALID DATA (B)

INPUT DATA (C)

WHZ

WPZ

The DQs go to High-Z if WE falls, and if WPZ is met,

will remain High-Z until CAS goes LOW with

WE HIGH (i.e., until a READ cycle is initiated).

WE may be used to disable the DQs to prepare

for input data in an EARLY WRITE cycle. The DQs

will remain High-Z until CAS goes LOW with

WE HIGH (i.e., until a READ cycle is initiated).

DON’T CARE

UNDEFINED

Figure 2

WE CONTROL OF DQs

AS4LC1M16

REV. 3/97

DS000020

Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

2-95

1 234 5 6 7...22

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