Datasheet > AS4C512M8D3L

AS4C512M8D3L

更新时间： 2022-02-26 12:11:07

品牌	Logo	应用领域
ALSC		/
页数	文件大小	规格书
86页	3307K
描述
AS4C512M8D3L - 78-ball FBGA PACKAGE

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AS4C512M8D3L 数据手册

4Gb DDR3L AS4C512M8D3L

512M x 8 bit DDR3L Synchronous DRAM (SDRAM)

Confidential

Advanced (Rev. 2.0, Aug. /2014)

Overview

Features

JEDEC Standard Compliant

The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs is

double data rate architecture to achieve high-speed

operation. It is internally configured as an eight bank

DRAM.

The 4Gb chip is organized as 64Mbit x 8 I/Os x 8 bank

devices. These synchronous devices achieve high

speed double-data-rate transfer rates of up to 1600

Mb/sec/pin for general applications.

The chip is designed to comply with all key DDR3L

DRAM key features and all of the control and address

inputs are synchronized with a pair of externally

supplied differential clocks. Inputs are latched at the

cross point of differential clocks (CK rising and CK#

falling). All I/Os are synchronized with differential DQS

pair in a source synchronous fashion.

These devices operate with a single 1.35V -0.067V

/+0.1V power supply and are available in BGA

packages.



Power supplies: V_DD& V_DDQ= +1.35V

Backward compatible to V_DD& V_DDQ= 1.5V ±0.075V

Operating temperature:

- Commercial (Extended) (0 ~ 95°C)

- Industrial (-40 ~ 95°C)

Supports JEDEC clock jitter specification

Fully synchronous operation

Fast clock rate: 800MHz

Differential Clock, CK & CK#

Bidirectional differential data strobe

- DQS & DQS#

8 internal banks for concurrent operation

8n-bit prefetch architecture

Internal pipeline architecture



Precharge & active power down

Programmable Mode & Extended Mode registers

Additive Latency (AL): 0, CL-1, CL-2

Programmable Burst lengths: 4, 8

Burst type: Sequential / Interleave

 Output Driver Impedance Control

 8192 refresh cycles / 64ms

- Average refresh period

7.8μs @ -40℃≦TC≦ +85℃

3.9μs @ +85℃＜TC≦ +95℃

 Write Leveling

 OCD Calibration

 Dynamic ODT (Rtt_Nom & Rtt_WR)

RoHS compliant



Auto Refresh and Self Refresh

78-ball 9 x 10.5 x 1.2mm FBGA package

- All parts are ROHS Compliant

Table 1. Speed Grade Information

Speed Grade

Clock Frequency

CAS Latency

t_RCD

t_RP

(ns)

DDR3L-1600

800 MHz

13.75

Table 2. Ordering Information

Product part No

Org

Temperature

Package

AS4C512M8D3L-12BCN

AS4C512M8D3L-12BIN

512M x 8 Commercial (Extended)

0°C to 95°C

512M x 8 Industrial

-40°C to 95°C (Extended)

78-ball FBGA

Confidential

Rev. 2.0

Aug. /2014

123 4 5 6 7...86

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