Datasheet > AS4C512M8D3L-12BIN

AS4C512M8D3L-12BIN

更新时间： 2022-02-26 12:11:07

品牌	Logo	应用领域
ALSC		/
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86页	3307K
描述
Fully synchronous operation

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4Gb DDR3L AS4C512M8D3L

Figure 65. Synchronous ODT Timing Example

(AL = 3; CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6)

T10

T11

T12

T13

T14

T15

CK#

CKE

ODT

AL = 3

CWL - 2

ODTH4, min

ODTLoff = CWL + AL - 2

ODTLon = CWL + AL - 2

t_AOF

t_AON

(min)

DRAM_RTT

RTT_NOM

t_AON

t_AOF

(max)

TRANSITIONING DATA

Don't Care

Figure 66. Synchronous ODT example with BL = 4, WL = 7

T10

T11

T12

T13

T14

T15

T16

T17

CK#

CKE

ODTH4min

NOP

ODTH4

NOP

ODTH4

NOP

WRS4

NOP

COMMAND

ODT

ODTLoff = WL - 2

ODTLon = WL - 2

ODTLoff = WL - 2

ODTLon = WL - 2

t_AOF

t_AON

t_AOF

(min)

t_AON

(max)

(min)

RTT_NOM

DRAM_RTT

t_AON

(max)

t_AOF

(max)

TRANSITIONING DATA

Don't Care

Figure 67. Dynamic ODT Behavior with ODT being asserted before and after the write

T10

T11

T12

T13

T14

T15

T16

T17

CK#

NOP

WRS4

VALID

NOP

COMMAND

ADDRESS

ODTH4

ODTLoff

ODTH4

ODT

RTT

ODTLon

ODTLcwn4

t_AON

t_ADC

(min)

t_AOF

(min)

t_ADC

(min)

RTT_NOM

RTT_WR

RTT_NOM

t_ADC

(max)

t_AOF

(max)

t_AON

t_ADC

(max)

ODTLcnw

DQS, DQS#

Din

n+1

Din

n+2

Din

n+3

TRANSITIONING DATA

Don't Care

NOTES:

Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high and to the registration of the Write command.

In this example, ODTH4 would be satisfied if ODT went low at T8 (4 clocks after the Write command).

Confidential

Rev. 2.0

Aug. /2014

1...77 78 798081 82 83...86

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