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AS29LV016JBRGR-70/XT PDF预览

AS29LV016JBRGR-70/XT

更新时间： 2024-02-19 20:33:27
品牌 Logo 应用领域
AUSTIN 闪存内存集成电路
页数 文件大小 规格书
40页 408K
描述
16 Megabit (2M x 8-Bit / 1M x 16-Bit) CMOS 3.0 Volt-Only Boot Sector Flash Memory

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AS29LV016JBRGR-70/XT 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：TSOP1包装说明：TSOP1, TSSOP56,.8,20
针数：48Reach Compliance Code：compliant
ECCN代码：3A001.A.2.CHTS代码：8542.32.00.51
风险等级：5.2Is Samacsys：N
最长访问时间：70 ns其他特性：BOTTOM BOOT BLOCK
备用内存宽度：8启动块：BOTTOM
命令用户界面：YES通用闪存接口：YES
数据轮询：YESJESD-30 代码：R-XDSO-G48
长度：18.4 mm内存密度：16777216 bit
内存集成电路类型：FLASH内存宽度：16
功能数量：1部门数/规模：1,2,1,31
端子数量：48字数：1048576 words
字数代码：1000000工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：1MX16封装主体材料：UNSPECIFIED
封装代码：TSOP1封装等效代码：TSSOP56,.8,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V编程电压：3 V
认证状态：Not Qualified就绪/忙碌：YES
座面最大高度：1.2 mm部门规模：16K,8K,32K,64K
最大待机电流：0.00001 A子类别：Flash Memories
最大压摆率：0.03 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED切换位：YES
类型：NOR TYPE宽度：12 mm
Base Number Matches：1

AS29LV016JBRGR-70/XT 数据手册

 浏览型号AS29LV016JBRGR-70/XT的Datasheet PDF文件第3页浏览型号AS29LV016JBRGR-70/XT的Datasheet PDF文件第4页浏览型号AS29LV016JBRGR-70/XT的Datasheet PDF文件第5页浏览型号AS29LV016JBRGR-70/XT的Datasheet PDF文件第7页浏览型号AS29LV016JBRGR-70/XT的Datasheet PDF文件第8页浏览型号AS29LV016JBRGR-70/XT的Datasheet PDF文件第9页 
COTS PEM  
BOOT SECTOR FLASH  
Austin Semiconductor, Inc.  
AS29LV016J  
DEVICE BUS OPERATIONS  
This section describes the requirements and use of the device bus operations, which are initiated through the internal  
command register. The command register itself does not occupy any addressable memory location. The register is composed  
of latches that store the commands, along with the address and data information needed to execute the command. The  
contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the  
device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The  
following subsections describe each of these operations in further detail.  
Table 1: AS29LV016J Device Bus Operations  
DQ8-DQ15  
DQ0-  
DQ7  
DOUT  
BYTE#  
=VIH  
BYTE#  
=VIL  
Address1  
AIN  
Operation  
CE#  
L
OE#  
L
WE#  
H
RESET#  
WP#  
X
DOUT  
Read  
H
H
DQ8-DQ14= High Z,  
DQ15=A-1  
AIN  
Write  
L
H
L
(Note 3)  
(Note 4) (Note 4)  
Standby  
Vcc 0.3V  
X
H
X
X
H
X
Vcc 0.3V  
X
X
X
X
X
X
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Output Disable  
Reset  
L
H
L
X
Sector Protect2,3  
VID  
L
H
L
(Note 4)  
(Note 4)  
X
X
X
Sector Address,  
A6=L, A1=H, A0=L  
Sector Address,  
A6=H, A3=A2=L,  
A1=H, A0=L  
AIN  
Sector Unprotect2.3  
Temporary Sector Unprotect  
Legend:  
VID  
VID  
L
H
X
L
H
X
X
X
(Note 4) (Note 4)  
High-Z  
L= Logic Low = VIL , H=Logic High=V IH , V ID =12.0 0.ꢀV, ꢁ=Donꢂt Care, AIN =Address In, DIN = Data In, DOUT =Data Out  
Notes:  
1. Addresses are A19:A0 in word mode (BYTE# = VIH ), A19:A-1 in byte mode (BYTE# = VIL  
)
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Protection /  
Unprotection on page 11.  
3. If WP# = VIL, the outermost sector remains protected (determined by device configuration). If WP# = VIH, the outermost sector protection  
depends on whether the sector was last protected or unprotected using the method described in Section 7.10, Sector Group Protection/  
Unprotection on page 21. The WP# contains an internal pull-up; when unconnected, WP is at VIH.  
4. DIN or DOUT as required by command sequence, data polling, or sector group protection algorithm.  
WORD / BYTE CONFIGURATION  
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE#  
pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.  
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled  
by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address  
function.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS29LV016J  
Rev. 0.0 02/09  
6
1...3456789...40

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