Datasheet > APVV-640.0MHZ-R-C-T

APVV-640.0MHZ-R-C-T

更新时间： 2022-12-01 19:48:05

品牌	Logo	应用领域
ABRACON		/
页数	文件大小	规格书
2页	1190K
描述
CMOS Output Clock Oscillator, 640MHz Nom, CERAMIC, SMD, 6 PIN

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APVV-640.0MHZ-R-C-T 数据手册

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CERAMIC SMD VOLTAGE CONTROL CRYSTAL OSCILLATOR

APVV SERIES

FEATURES:

: PRELIMINARY

5.0 x 7.0 x 1.8mm

APPLICATIONS:

• Sub 1pS ( 12kHz - 20MHz )

• SONET, Fiber Channel, SERDES

HDTV, OBSAI, CPRI, PCI Express, 1394

• CMOS, PECL or LVDS Output

• Low Jitter

• Low Power ( 2.5, 3.3V )

• Wide Pull Range

STANDARD SPECIFICATIONS: PARAMETERS

Frequency Range

38 MHz to 640 MHz

Operating Temperature

Storage Temperature

Frequency Pull Range

Pull Range Linearity

0°C to + 70°C (see options)

-55°C to +125°C

± 50 ppm (see options)

10% Max

Overall Frequency Stability

Supply Voltage (Vdd)

Phase Jitter RMS ^{(12KHz-20MHz)}

Period Jitter (peak to peak)

Tri-State Function

± 50 ppm max. (see options)

2.25V to 3.63 (2.5V to 3.3V ± 10%)

0.5pS Typ, 1pS Max

20pS typ., 30pS max up to 320 MHz; 50pS typ., 70pS max 321MHz to 640MHz

For CMOS and LVDS = "1" (VIH ³ 0.7* Vdd) or open: Oscillation;

"0" (VIL < 0.3* Vdd): No oscillation/Hi Z

For PECL (See TriState Pin Operation table) = P Option (Standard PECL OE)

"0" (VIL < 0.3* Vdd): or Open: Oscillation; "1" (VIH ³ 0.7* Vdd): No oscillation/Hi Z

P1 Option = "1" (VIH ³ 0.7* Vdd) or open: Oscillation;

"0" (VIL < 0.3* Vdd): No oscillation/Hi Z

PECL

65mA max (for 38MHz<Fo<320MHz), 90mA max (320MHz<Fo<640MHz)

45% min, 50% typical, 55% max.

Supply Current (I_DD)

Symmetry (Duty Cycle)

Output Logic High

Output Logic Low

Rise time

V_DD-1.025V min, V_DD-0.880V max.

V_DD-1.810V min, V_DD-1.620V max.

1.5ns max, 0.6nSec typical

Fall time

1.5ns max, 0.6nSec typical

CMOS

30mA max (38MHz<Fo<320MHz)

45% min, 50% typ, 55% max,

Supply Current

Symmetry (Duty Cycle)

Rise/ Fall Time

LVDS

(0.3V ~ 3.0V w/15 pF load) 0.7nS Typ.; (20%-80% w/50Ω Load) 0.3nS Typ.

45mA max(for 38MHz<Fo<320MHz), 70mA max (320MHz<Fo<640MHz)

Supply Current (I_DD)

Output Clock Duty Cycle @ 1.25V

Output Differential Voltage (V_OD)

45% min, 50% typical, 55% max

247mV min, 355mV typical, 454mV max

-50mV min, 50mV max

VDD Magnitude Change (∆V_OD

)

Output High Voltage

Output Low Voltage

Offset Voltage [R_L= 100

V_OH= 1.6V max, 1.4V typical

V_OL= 0.9V min, 1.1V typical

Ω

]

V_OS= 1.125V min, 1.2V typical, 1.375V max

∆V_OS= 0mV min, 3mV typical, 25mV max

±10µA max, ±1µA typical

Offset Magnitude Voltage[RL = 100

Power-off Leakage (I_OXD) [Vout=VDD or GND, VDD=0V]

Differential Clock Rise Time (t_r) [R_L=100 , CL=10pF]

Differential Clock Fall Time (t_f) [R_L=100 , CL=10pF]

Ω]

Ω

0.7ns typical, 1.0ns max

ABRACON IS

ISOIS9O009100/1Q:2S0900800

CERTIFIED

30332 Esperanza, Rancho Santa Margarita, California 92688

tel 949-546-8000 | fax 949-546-8001 | www.abracon.com

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