Datasheet > AN87196CB

AN87196CB

更新时间： 2024-01-31 21:17:37

品牌	Logo	应用领域
英特尔 - INTEL		微控制器
页数	文件大小	规格书
33页	451K
描述
ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0

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数据手册

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AN87196CB 数据手册

87C196CA/87C196CB

Symbol

Name and Function

Main Supply Voltage ( 5V).

SS SS1

Digital circuit ground (0V). There are 7 V pins CB (4 on CA), all of which MUST be

connected to a single ground plane.

REF

Reference for the A/D converter ( 5V). V

is also the supply voltage to the analog

REF

portion of the A/D converter and the logic used to read Port 0. Must be connected for

A/D and Port 0 to function.

ANGND

Reference ground for the A/D converter. Must be held at nominally the same potential

as V

Programming voltage for EPROM parts. It should be 12.5V for programming. It is

also the timing pin for the return from powerdown circuit. Connect this pin with a 1 mF

capacitor to V and a 1Mohm resistor to V . If this function is not used, V may be

tied to V

XTAL1

XTAL2

RESET

Input of the oscillator inverter and the internal clock generator.

Output of the Oscillator Inverter.

Reset input to the chip. Input low for at least 16 state times will reset the chip. The

subsequent low to high transition resynchronizes CLKOUT and commences a

10-state time sequence in which the PSW is cleared, bytes are read from 2018H,

201Ah and 201CH (if enabled) loading the CCB’s, and a jump to location 2080H is

executed. Input high for normal operation. RESET has an internal pullup.

NMI

A positive transition causes a non-maskable interrupt vector through memory location

203EH. If not used, this pin should be tied to V . May be used by Intel Evaluation

boards.

Input for memory select (External Access). EA equal to a high causes memory

accesses to locations 0FF2000H through 0FFFFFFH to be directed to on-chip

EPROM/ROM. EA equal to a low causes accesses to these locations to be directed

e a

to off-chip memory. EA

Mode. EA is latched at reset.

12.5V causes execution to begin in the Programming

PLLEN

(196CB only)

Selects between PLL mode or PLL bypass mode. This pin must be either tied high or

1, places a 4x PLL at the input

of the crystal oscillator. Allows for a low frequency crystal to drive the device (i.e.,

low. PLLEN pin

0, bypass PLL mode. PLLEN pin

5 MHz

20 MHz operation).

P6.4–6.7/SSIO

Dual function I/O ports have a system function as Synchronous Serial I/O. Two pins

are clocks and two pins are data providing for full duplex capability. Also LSIO when

not used as SSIO.

P6.3/T1DIR

(CB only)

Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it

may also be used as a TIMER1 Direction input. The TIMER1 will increment when this

pin is high and decrements when this pin is low.

P6.2/T1CLK

(CB only)

Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however may

also be used as a TIMER1 Clock input. The TIMER1 will increment or decrement on

both positive and negative edges of this pin.

P6.0–6.1/EPA8–9 Dual function I/O port pins. Primary function is that of bidirectional I/O. System

function is that of High Speed capture and compare.

1...4 5 678 9 10...33

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