82527
SERIAL COMMUNICATIONS CONTROLLER
CONTROLLER AREA NETWORK PROTOCOL
Automotive
Y
Y
Y
Y
Supports CAN Specification 2.0
Ð Standard Data and Remote Frames
Ð Extended Data and Remote Frames
Programmable Bit Rate
Y
Y
Y
Y
Y
Y
Y
Y
Y
Programmable Clock Output
Flexible Interrupt Structure
Flexible Status Interface
Programmable Global Mask
Ð Standard Message ldentifier
Ð Extended Message ldentifier
Configurable Output Driver
Configurable Input Comparator
Two 8-Bit Bidirectional I/O Ports
44-Lead PLCC Package
15 Message Objects of 8-Byte Data
Length
Ð 14 Tx/Rx Buffers
Ð 1 Rx Buffer with Programmable Mask
Y
Flexible CPU Interface
Ð 8-Bit Multiplexed
Ð 16-Bit Multiplexed
Ð 8-Bit Non-Multiplexed
(Synchronous/Asynchronous)
Ð Serial Interface
44-Lead QFP Package
Pinout Compatibility with the 82526
The 82527 serial communications controller is a highly integrated device that performs serial communication
according to the CAN protocol. It performs all serial communication functions such as transmission and
reception of messages, message filtering, transmit search, and interrupt search with minimal interaction from
the host microcontroller, or CPU.
The 82527 is Intel’s first device to support the standard and extended message frames in CAN Specification
2.0 Part B. It has the capability to transmit, receive, and perform message filtering on extended message
frames. Due to the backwardly compatible nature of CAN Specification 2.0, the 82527 also fully supports the
standard message frames in CAN Specification 2.0 Part A.
The 82527 features a powerful CPU interface that offers flexibility to directly interface to many different CPUs.
It can be configured to interface with CPUs using an 8-bit multiplexed, 16-bit multiplexed, or 8-bit non-multi-
plexed address/data bus for Intel and non-Intel architectures. A flexible serial interface (SPI) is also available
when a parallel CPU interface is not required.
The 82527 provides storage for 15 message objects of 8-byte data length. Each message object can be
configured as either transmit or receive except for the last message object. The last message object is a
receive-only buffer with a special mask design to allow select groups of different message identifiers to be
received.
The 82527 also implements a global masking feature for message filtering. This feature allows the user to
globally mask any identifier bits of the incoming message. The programmable global mask can be used for
both standard and extended messages.
The 82527 PLCC offers hardware, or pinout, compatibility with the 82526. It is pin-to-pin compatible with the
82526 except for pins 9, 30, and 44. These pins are used as chip selects on the 82526 and are used as CPU
interface mode selection pins on the 82527.
The 82527 is fabricated using Intel’s reliable CHMOS III 5V technology and is available in either 44-lead PLCC
b
a
or 44-lead QFP for the automotive temperature range ( 40 C to 125 C).
§
§
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
December 1995
Order Number: 272250-006
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