AN601
Vishay Siliconix
Unclamped Inductive Switching Rugged MOSFETs
For Rugged Environments
The evolution of the power MOSFET has resulted in a very
Symbols and Definitions
rugged transistor. The semiconductor industry defines this
ruggedness as the capability to withstand avalanche currents
whensubjectedtounclampedinductiveswitching. Historically,
MOSFET manufacturers chose to quantify ruggedness, not
based principally on individual performance, but rather on
comparative performance with other manufacturers. Siliconix
has optimized the cell structure of power MOSFETs, resulting
in a new class of extremely rugged devices. Today’s
avalanche-rated MOSPOWER FET exhibits a ruggedness
that far exceeds the performance of any power MOSFET of
earlier years.
Whenever possible, symbols and definitions established by
the JEDEC Committee, JC-25, are used in this article. To clear
up any discrepancies, however, the following list describes
symbols used frequently in this article.
IO the peak current reached during avalanche
tAV the time duration of the avalanche phenomenon
L
the value of inductance
V(BR)eff the breakdown voltage in avalanche
What is Unclamped Inductive Switching?
This application note reviews the history of unclamped
inductive switching (UIS) and examines various theories
pertaining to failure. It further identifies what appears to be two
related mechanisms — thermal and bipolar — believed to be
responsible for failure during unclamped inductive switching
and concludes by recommending how a power MOSFET
should be qualified for ruggedness in the data sheet.
Whenever current through an inductance is quickly turned off,
the magnetic field induces a counter electromagnetic force
(EMF) that can build up surprisingly high potentials across the
switch. Mechanical switches often have spark-suppression
circuitstoreducetheseharmfuleffectsthatresultwhencurrent
is suddenly interrupted. However, when transistors are used
as the switches, the full buildup of this induced potential may
far exceed the rated breakdown (V(BR)DSS) of the transistor,
thus resulting in catastrophic failure.
If we know the size of the inductor, the amount of current being
switched, and the speed of the switch, the expected potential
may be easily calculated as
Two failure modes exist when MOSFETs are subjected to UIS.
In this article, these failure mechanisms are labelled as either
active or passive. The first, or active mode, results when the
avalanche current forces the parasitic bipolar transistor into
conduction. The second, or passive mode, results when the
instantaneous chip temperature reaches a critical value.[1] At
this elevated temperature, a “mesoplasma”* forms within the
parasitic npn bipolar transistor and causes catastrophic
thermal runaway. In either case, the MOSFET is destroyed.
The passive mechanism is, therefore, identified as that failure
mode not directly attributed to avalanche currents.
V
=
L di/dt + VDD
(1)
where
L
=
=
=
the inductance (H)
di/dt
VDD
rate of change of current (A/s)
the supply voltage (V)
*A “mesoplasma,” according to Ghandhi, takes the form of a glowing red spot having an average temperature in excess of 650_C and a peak
core temperature in excess of 1000_C. This mesoplasma is a result of regenerative thermal runaway.
Document Number: 70572
15-Feb-94
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