Using the ABEL Tools of PAC-Designer
with Power Manager Devices
May 2003
Application Note AN6052
Introduction
Lattice Semiconductor’s PAC-Designer® software provides the LogiBuilder™ interface for the development of
sequential and logic designs for Power Manager devices. While the LogiBuilder interface is very capable of
addressing a wide variety of monitoring and sequencing applications, occasionally a design will require extended
functionality. For example implementing a “watch dog” timer or combining multiple functions within a state of the
state-machine to increase the efficiency of the embedded CPLD can be realized by using the ABEL tools.
PAC-Designer generates ABEL code from the LogiBuilder design because ABEL is a mature language that sup-
ports optimal fitting of logic into CPLDs that contain only a few macrocells. VHDL on the other hand is a language
that is more suited to system designs utilizing hundreds or thousands of macrocells. Fortunately, PAC-Designer
has the built-in capability to support user-modified ABEL compilation and simulation. In this application note, we
will cover the ABEL-flow process, a review of the timers, and demonstrate some features of the Power Manager
devices with examples. Additional information on the ABEL language is available in other manuals (see the refer-
ence list).
Figure 1. ABEL Process Flow Chart
Standard LogiBuilder Flow
Custom ABEL Flow
Edit Analog
Pin Names, Trip Points,
Clock & Timer, and Output Settings
Step 1
Step 4
Step 5
Edit ABEL code
Compile ABEL Design
Enter LogiBuilder Sequence
Step 2
Step 3
Compile LogiBuilder Design which
Generates ABEL Code
NO
Compile
Success
YES
YES
Simulate ABEL Design
Modify
ABEL
Step 6
NO
NO
Simulation
Success
Standard Simulate, Download,
Debug, and Export
Steps
YES
Step 7
Download Design to Device
NO
Test
Success
YES
Step 8
Export JEDEC File
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