Datasheet > AMS73CAG01408RAUJI9

AMS73CAG01408RAUJI9

更新时间： 2022-10-09 17:13:05

品牌	Logo	应用领域
奥地利微 - AMS		动态存储器双倍数据速率
页数	文件大小	规格书
31页	683K
描述
HIGH PERFORMANCE 1Gbit DDR3 SDRAM

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AMS73CAG01808RA

Mode Register MR0

The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It con-

trols burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge

power-down, which include various vendor specific options to make DDR3 SDRAM useful for various appli-

cations. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0, BA1 and BA2, while

controlling the states of address pins according to the table below.

Address Field

BA2

BA1

BA0

A12

A11

A10

0*¹

Mode Register 0

0*¹

DLL TM

CAS Latency

RBT

PPD

Read Burst Type

Nibble Sequential

Interleave

mode

Normal

Test

DLL Reset

8 (Fixed)

4 or 8(on the fly)

4 (Fixed)

Yes

Reserved

DLL Control for

Precharge PD

Write recovery for autoprecharge

A12

CAS Latency

A6 A5 A4

A11

A10

WR(cycles)

Reserved

Latency

Slow exit (DLL off)

Fast exit (DLL on)

Reserved

5^*2

6^*2

7^*2

BA1

BA0

MRS mode

MR0

8^*2

MR1

10^*2

MR2

12^*2

11(Optional for

DDR3-1600)

MR3

Reserved

*1 : BA2 and A13 are reserved for future use and must be programmed to 0 during MRS.

*2 : WR(write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the

next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR value in the mode register must be programmed to be equal or

larger than WRmin. The programmed WR value is used with tRP to determine tDAL.

AMS73CAG01808RA Rev. 1.0 December 2010

1...4 5 678 9 10...31

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