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AMMP-6120-TR2 PDF预览

AMMP-6120-TR2

更新时间： 2024-02-10 17:45:01
品牌 Logo 应用领域
安华高科 - AVAGO 射频微波倍频器
页数 文件大小 规格书
7页 282K
描述
8-24 GHz x2 Frequency Multiplier 5x5mm Surface Mount Package

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AMMP-6120-TR2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：LCC8,.2SQ,28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.32
特性阻抗：50 Ω构造：COMPONENT
最大输入功率 (CW)：15 dBmJESD-609代码：e4
安装特点：SURFACE MOUNT端子数量：8
最大工作频率：24000 MHz最小工作频率：8000 MHz
封装主体材料：PLASTIC/EPOXY封装等效代码：LCC8,.2SQ,28
电源：5 V射频/微波设备类型：FREQUENCY DOUBLER
子类别：RF/Microwave Frequency Multipliers最大压摆率：120 mA
表面贴装：YES端子面层：Nickel/Gold (Ni/Au)
Base Number Matches：1

AMMP-6120-TR2 数据手册

 浏览型号AMMP-6120-TR2的Datasheet PDF文件第1页浏览型号AMMP-6120-TR2的Datasheet PDF文件第2页浏览型号AMMP-6120-TR2的Datasheet PDF文件第3页浏览型号AMMP-6120-TR2的Datasheet PDF文件第4页浏览型号AMMP-6120-TR2的Datasheet PDF文件第5页浏览型号AMMP-6120-TR2的Datasheet PDF文件第7页 
5
20  
18  
16  
14  
12  
10  
Fout=26GHz  
Fout=26GHz  
Vd=4.5V, Vg=-1.2V  
10  
15  
20  
25  
30  
35  
8
Vg=-1.2V, Vd=4.5V  
Vg=-1.2V, Vd=5.0V  
Vg=-1.4V, Vd=4.5V  
Vg=-1.4V, Vd=5.0V  
Vg=-1.2V, Vd=4.5V  
Vg=-1.2V, Vd=5.0V  
Vg=-1.4V, Vd=4.5V  
Vg=-1.4V, Vd=5.0V  
6
4
2
0
-11 -9  
-7  
-5  
-3  
-1  
1
3
5
7
9
11  
-11 -9  
-7  
-5  
-3  
-1  
1
3
5
7
9
11  
Input Power [1H] (dBm)  
Input Power [1H] (dBm)  
Figure 19 . 2H Output Power Vs Input Power @ Fout=26GHz  
Figure 20 . Fundamental Supp. Vs Input Power @ Fout=26GHz  
-50  
-60  
-70  
-80  
-90  
Fout=15.6GHz  
F1  
-100  
-110  
-120  
-130  
-140  
-150  
-160  
-170  
Active  
Balun  
M/N  
@ fo  
Filter  
@ 2fo  
S
Amp  
F2  
1.E+02  
1.E+03  
1.E+04  
1.E+05  
1.E+06  
1.E+07  
Oꢀset Frequency [Hz]  
Figure 21. SSB Phase Noise of frequency doubler  
(Pin=+2dBm, fout=15.6GHz)  
Figure 22. Top Level Schematic of Frequency doubler  
Biasing and Operation  
The frequency doubler MMIC consists of a balun. The The AMMP-6120 performance changes with Drain Voltage  
outputs of this balun feed the gates of balanced FETs and  
the drains are connected to form the single-ended output.  
(Vd) and Gate bias (Vg) as shown in the previous graphs.  
Improvements in output power or fundamental suppres-  
This results in fundamental frequency & odd harmon- sion performance are possible by optimizing the Vg from  
ics cancellation. The even harmonic drain currents are in -1.2V to -1.4V and/or Vd from 4.5 to 5.0V.  
phase and thus add in phase. The input matching network  
A simplified schematic of the frequency multiplier is  
(M/N) is designed to provide good match at fundamental  
shown in figure 22. The active balun circuit and the output  
frequencies and produces high impedance mismatch to  
amplifier of the circuit are self biased. The Vg negative bias  
higher harmonics.  
(below pinch off) is only applied to FETs ‘F1’ and ‘F2’. FETs  
‘F1’ and ‘F2’ have no significant contribution to total drain  
The AMMP-6120 is biased with a single positive drain  
supply Vdd and a single negative gate supply using sepa- current therefore Vg cannot be used to set drain current.  
rate bypass capacitors. It is normally biased with the drain  
supply connected to Vd and the gate supply connected to  
Vg. For most applications it is recommended to use a Vg  
=-1.2V to -1.4V and Vd=4.5V to 5.0V.  
It should only be used to optimize the output power  
and fundamental & higher harmonics suppression of the  
doubler.  
Refer to the Absolute Maximum Ratings table for allowed  
DC and thermal conditions.  
The RF input and output ports are AC coupled thus no DC  
voltage is present at either port. The ground connection is  
made via the package base.”  
6
1...34567

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