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AMMC-6232-W50 PDF预览

AMMC-6232-W50

更新时间: 2024-02-23 20:35:54
品牌 Logo 应用领域
安华高科 - AVAGO 放大器射频微波功率放大器
页数 文件大小 规格书
8页 1398K
描述
18000MHz - 32000MHz RF/MICROWAVE NARROW BAND MEDIUM POWER AMPLIFIER, DIE

AMMC-6232-W50 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:DIE OR CHIP
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.33.00.01风险等级:5.71
构造:COAXIAL增益:23 dB
最大输入功率 (CW):15 dBm功能数量:1
最大工作频率:32000 MHz最小工作频率:18000 MHz
封装等效代码:DIE OR CHIP电源:4 V
射频/微波设备类型:NARROW BAND MEDIUM POWER子类别:RF/Microwave Amplifiers
最大压摆率:150 mABase Number Matches:1

AMMC-6232-W50 数据手册

 浏览型号AMMC-6232-W50的Datasheet PDF文件第2页浏览型号AMMC-6232-W50的Datasheet PDF文件第3页浏览型号AMMC-6232-W50的Datasheet PDF文件第4页浏览型号AMMC-6232-W50的Datasheet PDF文件第5页浏览型号AMMC-6232-W50的Datasheet PDF文件第6页浏览型号AMMC-6232-W50的Datasheet PDF文件第8页 
AMMC-6232 Application and Usage  
Biasing and Operation  
To VDD DC supply  
TheꢀAMMC-6232ꢀisꢀnormallyꢀbiasedꢀwithꢀaꢀpositiveꢀdrainꢀ  
supplyꢀ connectedꢀ toꢀ theꢀ VD1ꢀ andꢀ VD2ꢀ padsꢀ throughꢀ  
bypassꢀ capacitorꢀ asꢀ shownꢀ inꢀ Figuresꢀ 15ꢀ andꢀ 16.ꢀ Theꢀ  
recommendedꢀdrainꢀvoltageꢀandꢀgateꢀvoltageꢀforꢀgeneralꢀ  
usageꢀ isꢀ 4Vꢀ andꢀ -0.95Vꢀ respectively.WithVdd=4V,Vg=-  
0.95V,thecorrespondingdraincurrentisapproximatelyꢀ  
135mA.ꢀ Itꢀ isꢀ importantꢀ toꢀ haveꢀ atꢀ leastꢀ 0.1upFꢀ bypassꢀ  
capacitorꢀ andꢀ theꢀ capacitorꢀ shouldꢀ beꢀ placedꢀ asꢀ closeꢀ  
toꢀ theꢀ componentꢀ asꢀ possible.ꢀ Aspectsꢀ ofꢀ theꢀ amplifierꢀ  
performanceꢀmayꢀbeꢀimprovedꢀoverꢀaꢀnarrowerꢀbandwidthꢀ  
byꢀ applicationꢀ ofꢀ additionalꢀ conjugate,ꢀ linearity,ꢀ orꢀ lowꢀ  
noiseꢀ(Topt)ꢀmatching.  
0.1 uF Capacitor  
VD1  
VD2  
RF OUTPUT  
RF INPUT  
AMMC-6232  
To VGate DC supply  
Afterꢀ adjustingꢀ theꢀ gateꢀ biasꢀ toꢀ obtainꢀ 135mAꢀ atꢀ Vddꢀ  
=ꢀ 4V,ꢀ theꢀ AMMC-6232ꢀ canꢀ beꢀ safelyꢀ biasedꢀ atꢀ Vdd=ꢀ  
3Vꢀ orꢀ 5Vꢀ (whileꢀ fixingꢀ theꢀ gateꢀ bias)ꢀ asꢀ desired.ꢀ Atꢀ 4V,ꢀ  
theꢀ performanceꢀ isꢀ anꢀ optimalꢀ compromiseꢀ betweenꢀ  
powerconsumption,gainandpower/linearity.Itꢀisꢀbothꢀ  
applicableꢀtoꢀbeꢀusedꢀasꢀaꢀlowꢀnoiseꢀblockꢀorꢀdriver.ꢀAtꢀ3V,ꢀ  
theꢀamplifierꢀisꢀidealꢀasꢀaꢀfrontꢀendꢀlowꢀnoiseꢀblockꢀwhereꢀ  
linearityꢀ isꢀ notꢀ highlyꢀ required.ꢀ Atꢀ 5V,ꢀ theꢀ amplifierꢀ canꢀ  
provide~2dBmoreoutputpowerforLOortransmitterꢀ  
driverꢀapplicationsꢀwhereꢀhighꢀoutputꢀpowerꢀandꢀlinearityꢀ  
areꢀoftenꢀrequired.  
Figure 19. Gate Bias Combined Together  
To VDD DC supply  
0.1 uF Capacitor  
VD1  
VD2  
RF OUTPUT  
RF INPUT  
AMMC-6232  
Theꢀ twoꢀ gateꢀ voltagesꢀ canꢀ beꢀ combinedꢀ asꢀ shownꢀ inꢀ  
Figureꢀ15ꢀorꢀseparatedꢀasꢀinꢀFigureꢀ16.ꢀCombiningꢀtheꢀtwoꢀ  
gateꢀ voltagesꢀ simplifiesꢀ theꢀ usageꢀ whereasꢀ separatingꢀ  
themꢀprovidesꢀflexibilityꢀtoꢀoverallꢀbiasingꢀscheme.  
Gold Plated Shim (Optional)  
To VG1 DC supply  
To VG2 DC supply  
Inbothcases,bondingwiresattheinputandoutputinꢀ  
theꢀrangeꢀofꢀ0.15nHꢀwouldꢀlikelyꢀimproveꢀtheꢀoverallꢀNoiseꢀ  
Figureꢀandꢀinput,ꢀoutputꢀmatchꢀatꢀmostꢀfrequencies.ꢀ  
Figure 20. Separated Gate Bias  
Noꢀgroundꢀwiresꢀareꢀneededꢀbecauseꢀgroundꢀconnectionꢀ  
isꢀmadeꢀwithꢀplatedꢀthrough-holesꢀtoꢀtheꢀbacksideꢀofꢀtheꢀ  
substrate.ꢀ  
Figure 21. Simplified High Linearity LNA Schematic  

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