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AM29DL800BT120FE

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品牌 Logo 应用领域
超微 - AMD 闪存
页数 文件大小 规格书
43页 545K
描述
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

AM29DL800BT120FE 数据手册

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PRELIMINARY  
Am29DL800B  
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)  
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory  
DISTINCTIVE CHARACTERISTICS  
Simultaneous Read/Write operations  
Sector protection  
— Host system can program or erase in one bank,  
then immediately and simultaneously read from  
the other bank  
— Hardware method of locking a sector to prevent  
any program or erase operation within that  
sector  
— Zero latency between read and write operations  
— Read-while-erase  
— Sectors can be locked in-system or via  
programming equipment  
Temporary Sector Unprotect feature allows code  
changes in previously locked sectors  
— Read-while-program  
Single power supply operation  
Top or bottom boot block configurations  
— Full voltage range: 2.7 to 3.6 volt read and write  
operations for battery-powered applications  
available  
Embedded Algorithms  
Manufactured on 0.35 µm process technology  
— Embedded Erase algorithm automatically  
pre-programs and erases sectors or entire chip  
— Compatible with 0.5 µm Am29DL800 device  
High performance  
— Embedded Program algorithm automatically  
programs and verifies data at specified address  
— Access times as fast as 70 ns  
Low current consumption (typical values  
Minimum 1,000,000 program/erase cycles  
at 5 MHz)  
guaranteed per sector  
— 7 mA active read current  
Package options  
— 44-pin SO  
— 21 mA active read-while-program or read-while-  
erase current  
— 48-pin TSOP  
— 48-ball FBGA  
— 17 mA active program-while-erase-suspended  
current  
Compatible with JEDEC standards  
— 200 nA in standby mode  
— Pinout and software compatible with  
single-power-supply flash standard  
— 200 nA in automatic sleep mode  
— Standard tCE chip enable access time applies to  
transition from automatic sleep mode to active  
mode  
— Superior inadvertent write protection  
Data# Polling and Toggle Bits  
Flexible sector architecture  
— Provides a software method of detecting  
program or erase cycle completion  
Two 16 Kword, two 8 Kword, four 4 Kword, and  
fourteen 32 Kword sectors in word mode  
Ready/Busy# output (RY/BY#)  
Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and  
fourteen 64 Kbyte sectors in byte mode  
— Hardware method for detecting program or  
erase cycle completion  
— Any combination of sectors can be erased  
— Supports full chip erase  
Erase Suspend/Erase Resume  
— Suspends or resumes erasing sectors to allow  
reading and programming in other sectors  
Unlock Bypass Program Command  
— Reduces overall programming time when  
issuing multiple program command sequences  
— No need to suspend if sector is in the other bank  
Hardware reset pin (RESET#)  
— Hardware method of resetting the device to  
reading array data  
This document contains information on a product under development at Advanced Micro Devices. The information  
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed  
product without notice.  
Publication# 21519 Rev: A Amendment/+3  
Issue Date: April 1998  

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