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AM1806EZCEA3 PDF预览

AM1806EZCEA3

更新时间: 2024-01-13 00:20:43
品牌 Logo 应用领域
德州仪器 - TI 双倍数据速率光电二极管
页数 文件大小 规格书
241页 1437K
描述
Sitara 处理器:Arm9,LPDDR,DDR2,显示 | ZCE | 361 | -40 to 105

AM1806EZCEA3 数据手册

 浏览型号AM1806EZCEA3的Datasheet PDF文件第1页浏览型号AM1806EZCEA3的Datasheet PDF文件第3页浏览型号AM1806EZCEA3的Datasheet PDF文件第4页浏览型号AM1806EZCEA3的Datasheet PDF文件第5页浏览型号AM1806EZCEA3的Datasheet PDF文件第6页浏览型号AM1806EZCEA3的Datasheet PDF文件第7页 
AM1806  
SPRS658BFEBRUARY 2010REVISED MAY 2010  
www.ti.com  
• Two Multichannel Buffered Serial Ports:  
– Transmit/Receive Clocks  
• One 64-bit General-Purpose/Watchdog Timer  
(Configurable as Two 32-bit General-Purpose  
Timers)  
• Two Enhanced Pulse Width Modulators  
(eHRPWM):  
– Two Clock Zones and 16 Serial Data Pins  
– Supports TDM, I2S, and Similar Formats  
– AC97 Audio Codec Interface  
– Telecom Interfaces (ST-Bus, H100)  
– 128-channel TDM  
– Dedicated 16-Bit Time-Base Counter With  
Period And Frequency Control  
– 6 Single Edge, 6 Dual Edge Symmetric or 3  
Dual Edge Asymmetric Outputs  
– Dead-Band Generation  
– PWM Chopping by High-Frequency Carrier  
– Trip Zone Input  
– FIFO buffers for Transmit and Receive  
• Video Port Interface (VPIF):  
– Two 8-bit SD (BT.656), Single 16-bit or Single  
Raw (8-/10-/12-bit) Video Capture Channels  
– Two 8-bit SD (BT.656), Single 16-bit Video  
Display Channels  
• Three 32-Bit Enhanced Capture Modules  
(eCAP):  
• Universal Parallel Port (uPP):  
– Configurable as 3 Capture Inputs or 3  
Auxiliary Pulse Width Modulator (APWM)  
outputs  
– Single Shot Capture of up to Four Event  
Time-Stamps  
– High-Speed Parallel Interface to FPGAs and  
Data Converters  
– Data Width on Each of Two Channels is 8- to  
16-bit Inclusive  
– Single Data Rate or Dual Data Rate Transfers  
– Supports Multiple Interfaces with START,  
ENABLE and WAIT Controls  
• 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)  
[ZCE Suffix], 0.65-mm Ball Pitch  
• Commercial or Extended Temperature  
• Community Resources  
• Real-Time Clock With 32 KHz Oscillator and  
Separate Power Rail  
• Three One 64-Bit General-Purpose Timers  
(Configurable as Two 32-Bit Timers)  
TI E2E Community  
TI Embedded Processors Wiki  
2
AM1806 ARM Microprocessor  
Copyright © 2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): AM1806  

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