AM1808
www.ti.com
SPRS653B–FEBRUARY 2010–REVISED APRIL 2011
AM1808 ARM Microprocessor
Check for Samples: AM1808
1 AM1808 ARM Microprocessor
1.1 Features
12
• Highlights
• Two External Memory Interfaces:
– EMIFA
– 375/456-MHz ARM926EJ-S™ RISC Core
– ARM9 Memory Architecture
– Programmable Real-Time Unit Subsystem
•
•
•
NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
16-Bit SDRAM With 128 MB Address
Space
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– Two External Memory Interfaces
– DDR2/Mobile DDR Memory Controller
– Three Configurable 16550 type UART
•
16-Bit DDR2 SDRAM With 512 MB
Address Space or
Modules
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
•
16-Bit mDDR SDRAM With 256 MB
Address Space
Card Interface with Secure Data I/O (SDIO)
• Three Configurable 16550 type UART Modules:
– With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
• LCD Controller
– Two Master/Slave Inter-Integrated Circuit
– USB 2.0 OTG Port With Integrated PHY
– One Multichannel Audio Serial Port
– 10/100 Mb/s Ethernet MAC (EMAC)
– Three 64-Bit General-Purpose Timers
– One 64-bit General-Purpose/Watchdog Timer
– TwoEnhanced Pulse Width Modulators
– Three 32-Bit Enhanced Capture Modules
• 375/456MHz ARM926EJ-S™ RISC MPU
• ARM926EJ-S Core
• Two Serial Peripheral Interfaces (SPI) Each
With Multiple Chip-Selects
• Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
Interfaces
• Two Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• One Host-Port Interface (HPI) With 16-Bit-Wide
Muxed Address/Data Bus For High Bandwidth
• Programmable Real-Time Unit Subsystem
– 32-Bit and 16-Bit (Thumb®) Instructions
– Single Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture
(PRUSS)
– Two Independent Programmable Realtime
– 16K-Byte Instruction Cache
Unit (PRU) Cores
– 16K-Byte Data Cache
– 8K-Byte RAM (Vector Table)
– 64K-Byte ROM
•
•
•
•
32-Bit Load/Store RISC architecture
4K Byte instruction RAM per core
512 Bytes data RAM per core
PRU Subsystem (PRUSS) can be disabled
via software to save power
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– 2 Channel Controllers
– 3 Transfer Controllers
– 64 Independent DMA Channels
– 16 Quick DMA Channels
•
Register 30 of each PRU is exported from
the subsystem in addition to the normal
R31 output of the PRU cores.
– Standard power management mechanism
•
•
Clock gating
Entire subsystem under a single PSC
clock gating domain
– Programmable Transfer Burst Size
• 128K-Byte On-Chip Memory
• 1.8V or 3.3V LVCMOS IOs (except for USB and
– Dedicated interrupt controller
– Dedicated switched central resource
DDR2 interfaces)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
5秒后页面跳转
全球首块英伟达H200交付 黄仁勋“送货上门”
常用8脚开关电源芯片型号大全
74HC04芯片引脚图及功能、应用电路图讲解
CR6842芯片参数、引脚配置、应用电路图详解
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
