Datasheet > AK7DCQ1-212.5000

AK7DCQ1-212.5000

更新时间： 2022-12-01 23:54:40

品牌	Logo	应用领域
ABRACON		输出元件
页数	文件大小	规格书
12页	2034K
描述
CRYSTAL OSCILLATOR, CLOCK, LVDS OUTPUT,

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AK7DCQ1-212.5000 数据手册

ClearClock™ | Ultra-Low Jitter 7.0 x 5.0mm XO

7.0 x 5.0 x 1.8 mm

RoHS/RoHS II Compliant

MSL = 1

AK7

ESD Sensitive

Electrical Characteristics Cont.

Parameters

Min.

V_dd-1.03

Typ.

Max.

V_dd-0.88

V_dd-1.60

1.60

Unit

Notes

V_OH

V_OL

V_OH

V_OL

V_OH

V_OL

LVPECL

R_L=50Ω to V_dd–2.0V

V_dd-1.85

Differential

1.40

1.10

0.74

0.00

0.75

0.35

0.70

Output High Voltage (V_OH

Output Low Voltage (V_OL)

)

LVDS

HCSL

R_L=100Ω between both outputs

0.90

0.40

0.85

0.15

0.93

0.45

0.78

R_L=50Ω to ground on each

output

-0.15

0.595

0.25

LVPECL

Output Voltage Swing

LVDS

0.620

0.7*(V_dd)

HCSL

Output Enable; or No Connect

Output Disable; High Impedance

Output Enable & Disable Control

0.3*(V_dd)

5.0

Output Enable Time

Output Disable Time

< 1

0.2

μs

Output Disable Current Consumption

< 10

μA OE ≤ 0.3V

@ V_dd=3.3V

LVPECL

LVDS

105

150

175

145

160

100

105

115

105

135

140

@ V_dd=2.5V

125

150

120

135

@ V_dd=3.3V

fsec

@ 200 MHz

@ V_dd=2.5V

@ V_dd=3.3V

@ V_dd=2.5V

@ V_dd=3.3V

@ V_dd=2.5V

RMS Phase Jitter ^{[Note 7, 8, 9]}

@ +25°C

HCSL

LVPECL

LVDS

(12kHz-20MHz BW)

@ V_dd=3.3V

fsec

@ 156.25 MHz

@ V_dd=2.5V

110

115

@ V_dd=3.3V

@ V_dd=2.5V

HCSL

Note 7:

Note 8:

Note 9:

Guaranteed by characterization; RMS Phase Jitter speciﬁcations are inclusive of any spurs

Phase jitter measured with Keysight E5052B Signal Source Analyzer

Refer to the next section for phase noise test setup and representative phase noise plots

5101 Hidden Creek Ln Spicewood TX 78669

Phone: 512-371-6159 | Fax: 512-351-8858

For terms and conditions of sales, please visit:

www.abracon.com

ABRACON IS

ISO9001-2015

CERTIFIED

REVISED: 04.15.2019

LLC

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