ClearClock™ | Ultra-Low Jitter 7.0 x 5.0mm XO
7.0 x 5.0 x 1.8 mm
RoHS/RoHS II Compliant
MSL = 1
AK7
ESD Sensitive
Pb
Electrical Characteristics Cont.
Parameters
Min.
Vdd-1.03
Typ.
Max.
Vdd-0.88
Vdd-1.60
1.60
Unit
Notes
VOH
VOL
VOH
VOL
VOH
VOL
LVPECL
RL=50Ω to Vdd–2.0V
Vdd-1.85
Differential
1.40
1.10
0.74
0.00
0.75
0.35
0.70
Output High Voltage (VOH
Output Low Voltage (VOL)
)
LVDS
HCSL
V
RL=100Ω between both outputs
0.90
0.40
0.85
0.15
0.93
0.45
0.78
RL=50Ω to ground on each
output
-0.15
0.595
0.25
LVPECL
Output Voltage Swing
V
V
LVDS
0.620
0.7*(Vdd)
HCSL
Output Enable; or No Connect
Output Disable; High Impedance
Output Enable & Disable Control
0.3*(Vdd)
5.0
Output Enable Time
Output Disable Time
< 1
ms
0.2
μs
Output Disable Current Consumption
< 10
95
μA OE ≤ 0.3V
@ Vdd=3.3V
70
80
LVPECL
LVDS
105
150
175
145
160
100
105
115
105
135
140
@ Vdd=2.5V
125
150
120
135
75
@ Vdd=3.3V
fsec
@ 200 MHz
@ Vdd=2.5V
@ Vdd=3.3V
@ Vdd=2.5V
@ Vdd=3.3V
@ Vdd=2.5V
RMS Phase Jitter [Note 7, 8, 9]
@ +25°C
HCSL
LVPECL
LVDS
(12kHz-20MHz BW)
80
90
@ Vdd=3.3V
fsec
@ 156.25 MHz
80
@ Vdd=2.5V
110
115
@ Vdd=3.3V
@ Vdd=2.5V
HCSL
Note 7:
Note 8:
Note 9:
Guaranteed by characterization; RMS Phase Jitter specifications are inclusive of any spurs
Phase jitter measured with Keysight E5052B Signal Source Analyzer
Refer to the next section for phase noise test setup and representative phase noise plots
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