AIC111
SLAS382 – JUNE 2003
www.ti.com
Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduring
storageor handling to prevent electrostatic damage to the MOS gates.
The AIC111 comes in a 32-pin QFN 5×5-mm package. A 32-pad solder ball bumped flip chip die that comes in waffle
packs or tape and reel is in preview and will be available 3rd quarter 2003.
AVAILABLE OPTIONS
PART NUMBER
AIC111RHB
PACKAGE
32-pin QFN (5 mm x 5 mm), in tube.
32-pin QFN (5 mm x 5 mm), tape and reel
AIC111RHBR
32-padwaffle scale chip package, bumped die in waffle pack (contact the factory for availability) – Preview,
AIC111YE
available 3rd quarter 2003
32-pad (WSCP) bumped die in tape and reel (contact the factory for availability) – Preview, available 3rd
AIC111YER
quarter2003
ABSOLUTE MAXIMUM RATINGS
overoperating free-air temperature range unless otherwise noted
(1)(2)
UNIT
Inputvoltage
AI or DI pins
–0.3 V to 4 V
–0.3 V to 4.5 V
100 mA
Power supply
VDD, power pins
Latch-uptolerance
JEDEC latch-up (EIA/JEDS78)
Operating free-air temperature range, T
0°C to 70°C
–15°C to 85°C
220°C to 230°C
–40°C to 125°C
65% R.H.
A
Functionaltemperaturerange
Reflow temperature range (flip chip)
Storage temperature range, T
stg
Storagehumidity
(1)
Stresses beyond those listed under absolutemaximumratings may cause permanent damage to the device. These are stress ratings only, and
functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.
Exposureto absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Specifications are assured operating at maximum device limits for QFN package only, unless otherwise specified.
ELECTRICAL CHARACTERISTICS
INPUT/OUTPUT, OPERATING TEMPERATURE AT 25°C
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Digital interface (see Notes 1 and 2)
BUF_DVDD (see Note 1)
3.6
V
V
V
V
V
V
V
V
V
High-level input voltage
Low-level input voltage
BUF_DVDD–0.2
BUF_DVSS+0.2
BUF_DVDD
IH
IL
High-level output voltage
Low-level output voltage
OH
OL
BUF_DVSS
Maximum allowed input voltage (AVIN)
Input impedance (AVIN) (see Note 3)
Input capacitance (AVIN)
Differential
450 mVpk
Nominal gain = 50x
20
5
kΩ
pF
Microphone bias voltage (MIC_VSUP)
Microphone bias resistor (MIC_BIAS)
20-µAmaximum
0.87
27
0.94
0.99
31
V
29.1
kΩ
Fixed Q
3/4 HB_VDD
HB_VDD
20 or 40
H-bridgeamplifieroutput
Outputresistance
DAC full scale output differential
V
PP
Adaptive Q
Differential, HB – V
= 1.3 V
Ω
DD
(1)
DVDD, VDD_OSC, and AVDD should be within 50 mV, preferably connected together.
AVSS1, 2, DVSS, and VSS_OSC should be within 50 mV, preferably connected together.
Maximum (0.9 V, DVDD –0.5 V) ≤ BUF_DVDD ≤3.6 V
Driving single-ended: Rin = R × [(1+A)/(2+A)], A = PGAC Gain (linear), R = 20.4 kΩ for A ≥ 4 or 20.4 kΩ × (4/A) for A<4.
Rin(min) = 17 kΩ (A=4), Rin(max) = 59.89 kΩ (A = 0.89), Rin(nom) = 20 kΩ (A = 50).
(2)
(3)
2