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AGLN010V5-UC36I PDF预览

AGLN010V5-UC36I

更新时间: 2024-01-05 13:55:29
品牌 Logo 应用领域
ACTEL 时钟可编程逻辑
页数 文件大小 规格书
140页 4325K
描述
Field Programmable Gate Array, 260 CLBs, 10000 Gates, 250MHz, 260-Cell, CMOS, PBGA36, 4 X 4 MM, 0.8 MM HEIGHT, 0.4 MM PITCH, UC-36

AGLN010V5-UC36I 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:4 X 4 MM, 0.8 MM HEIGHT, 0.4 MM PITCH, UC-36Reach Compliance Code:compliant
风险等级:5.85Is Samacsys:N
最大时钟频率:250 MHzJESD-30 代码:S-PBGA-B36
长度:3 mm可配置逻辑块数量:260
等效关口数量:10000输入次数:23
逻辑单元数量:260输出次数:23
端子数量:36最高工作温度:85 °C
最低工作温度:-40 °C组织:260 CLBS, 10000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装等效代码:BGA36,6X6,16封装形状:SQUARE
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:0.8 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.575 V
最小供电电压:1.425 V标称供电电压:1.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.4 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

AGLN010V5-UC36I 数据手册

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Revision 10  
®
IGLOO nano Low Power Flash FPGAs  
with Flash*Freeze Technology  
High-Performance Routing Hierarchy  
Features and Benefits  
Segmented, Hierarchical Routing and Clock Structure  
Low Power  
Advanced I/Os  
nanoPower Consumption—Industry’s Lowest Power  
1.2 V to 1.5 V Core Voltage Support for Low Power  
Supports Single-Voltage System Operation  
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages—up to 4 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS  
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V  
Low Power Active FPGA Operation  
Flash*Freeze Technology Enables Ultra-Low Power  
Consumption while Maintaining FPGA Content  
Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode  
Wide Range Power Supply Voltage Support per JESD8-B,  
Allowing I/Os to Operate from 2.7 V to 3.6 V  
Wide Range Power Supply Voltage Support per JESD8-12,  
Allowing I/Os to Operate from 1.14 V to 1.575 V  
I/O Registers on Input, Output, and Enable Paths  
Selectable Schmitt Trigger Inputs  
Small Footprint Packages  
As Small as 3x3 mm in Size  
Wide Range of Features  
Hot-Swappable and Cold-Sparing I/Os  
10,000 to 250,000 System Gates  
Up to 36 kbits of True Dual-Port SRAM  
Up to 71 User I/Os  
Programmable Output Slew Rate and Drive Strength  
Weak Pull-Up/-Down  
IEEE 1149.1 (JTAG) Boundary Scan Test  
®
Pin-Compatible Packages across the IGLOO Family  
Reprogrammable Flash Technology  
Clock Conditioning Circuit (CCC) and PLL†  
130-nm, 7-Layer Metal, Flash-Based CMOS Process  
Live-at-Power-Up (LAPU) Level 0 Support  
Single-Chip Solution  
Retains Programmed Design When Powered Off  
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System  
Performance  
Up to Six CCC Blocks, One with an Integrated PLL  
Configurable Phase Shift, Multiply/Divide, Delay  
Capabilities, and External Feedback  
Wide Input Frequency Range (1.5 MHz up to 250 MHz)  
Embedded Memory  
In-System Programming (ISP) and Security  
1 kbit of FlashROM User Nonvolatile Memory  
Secure ISP Using On-Chip 128-Bit Advanced Encryption  
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)  
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM  
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)  
True Dual-Port SRAM (except × 18 organization)  
®
FlashLock to Secure FPGA Contents  
1.2 V Programming  
Enhanced Commercial Temperature Range  
–20°C to +70°C  
Table 1 • IGLOO nano Devices  
IGLOO nano Devices  
AGLN010 AGLN015 AGLN020  
AGLN060 AGLN125 AGLN250  
1
AGLN030Z1 AGLN060Z AGLN125Z AGLN250Z  
IGLOO nano-Z Devices  
System Gates  
10K  
86  
260  
2
15K  
128  
384  
4
20K  
172  
520  
4
30K  
256  
768  
5
60K  
512  
1,536  
10  
125K  
1,024  
3,072  
16  
250K  
2,048  
6,144  
24  
Typical Equivalent Macrocells  
VersaTiles (D-flip-flops)  
Flash*Freeze Mode (typical, µW)  
2
RAM kbits (1,024 bits)  
18  
36  
36  
2
4,608-Bit Blocks  
4
8
8
FlashROM Bits  
1 k  
1 k  
1 k  
1 k  
1 k  
Yes  
1
1 k  
Yes  
1
1 k  
Yes  
1
2
Secure (AES) ISP  
2,3  
Integrated PLL in CCCs  
VersaNet Globals  
4
4
4
6
18  
18  
18  
I/O Banks  
2
3
3
2
2
2
4
Maximum User I/Os (packaged device)  
Maximum User I/Os (Known Good Die)  
34  
34  
49  
52  
52  
77  
83  
71  
71  
68  
71  
71  
68  
Package Pins  
UC/CS  
UC36  
QN48  
UC81,  
CS81  
QN68  
UC81, CS81  
QN48, QN68  
VQ100  
CS81  
CS81  
CS81  
QFN  
VQFP  
QN68  
VQ100  
VQ100  
VQ100  
Notes:  
1. AGLN030 is available in the Z feature grade only.  
2. AGLN030 and smaller devices do not support this feature.  
3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.  
4. For higher densities and support of additional features, refer to the IGLOO and IGLOOe handbooks.  
† AGLN030 and smaller devices do not support this feature.  
April 2010  
I
© 2010 Actel Corporation  

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