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AFEDRI8201PFBT PDF预览

AFEDRI8201PFBT

更新时间： 2024-02-09 12:58:56
品牌 Logo 应用领域
BB 商用集成电路
页数 文件大小 规格书
22页 238K
描述
IF ADC Front End for AM/FM and HD Radios

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AFEDRI8201PFBT 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：QFP-48
针数：48Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.81Is Samacsys：N
其他特性：IT ALSO REQUIRES 1.71V TO 1.89V SUPPLY商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：S-PQFP-G48JESD-609代码：e4
长度：7 mm湿度敏感等级：2
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmBase Number Matches：1

AFEDRI8201PFBT 数据手册

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ꢉꢠꢡ ꢃ ꢁꢇ ꢢꢣ ꢤꢥ  
www.ti.com  
SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005  
DETAILED DESCRIPTION  
The AFEDRI8201 consists of a general-purpose, 80MSPS, 12-bit analog-to-digital converter (ADC) with programmable input  
range, digital downconverter (DDC), and user programmable digital filters with 16-bit coefficients. It is designed to sample  
narrowband (up to 2.5MHz) IF signals and digitally mix, filter, and decimate the signals to baseband. The ADC integrates a  
programmable gain sample-and-hold amplifier that is variable over gains of 1x to 4x to change the full-scale input voltage range  
of the device from 1.0V peak to 0.25V peak. When the gain is changed, two sample periods may be needed for the output of  
the ADC to settle to the correct value.  
The DDC consists of a digital quadrature mixer followed by a CIC decimation filter and FIR filters (FIR1 and FIR2). The mixer  
frequency and initial phase are independently programmed by 32-bit control words. The quadrature mixer generates I and Q  
signals, each of which are decimated by the CIC filter. The CIC is a 5th-order Comb filter with a decimation factor that is  
programmable over a range of 8 to 1024. Each of the FIR filters adds an additional decimation factor of 2, for a total range of  
32 to 4096.  
The I and Q signals generated by the quadrature mixer are then passed on to the first FIR filter (FIR1). This decimate-by-two  
FIR filter can implement even, odd, halfband, and arbitrary impulse responses. The length of the filter response is dependent  
on the decimation factor of the CIC filter and the FIR filter response type, up to a maximum of 62 taps. Coefficients for multiple  
filter responses may be stored in the coefficient memory (up to 64 unique coefficients may be stored); responses can be changed  
by changing a control register to point the filter to a different section of coefficient memory.  
Following FIR1 are two parallel decimate-by-two FIR filters (FIR2A and FIR2B). These filters are similar to FIR1, but have twice  
the data and coefficient memory and can therefore realize longer filter responses. The responses of the FIR2A and FIR2B can  
be different from each other (with some limitations). In addition, FIR2A and FIR2B can be optionally interleaved to form a single  
extra-long FIR filter that can realize up to 251 taps.  
Control register information, as well as decimation filter coefficients, are written to the AFEDRI8201 through the industry-standard  
SPI control interface. The baseband output signals are transported through a high-speed serial interface that is compatible with  
the TI C5x/C6x DSP buffered serial ports (McBSP).  
The AFEDRI8201 also contains a 12-bit auxiliary digital-to-analog converter (DAC) which can be used for a number of purposes,  
including tuner automatic gain control or frequency control. Input data for the DAC may be sent either from the DSP through  
the serial data port or from a microcontroller through the SPI control interface.  
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