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AFE1103E/1K PDF预览

AFE1103E/1K

更新时间: 2024-01-30 05:38:25
品牌 Logo 应用领域
德州仪器 - TI 电信光电二极管电信集成电路
页数 文件大小 规格书
14页 337K
描述
DATACOM, DIGITAL SLIC, PDSO48, GREEN, PLASTIC, SSOP-48

AFE1103E/1K 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP48,.4
针数:48Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.73数据速率:1168 Mbps
JESD-30 代码:R-PDSO-G48长度:15.875 mm
功能数量:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3,5 V认证状态:Not Qualified
座面最大高度:2.79 mm子类别:Other Telecom ICs
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:DIGITAL SLIC
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

AFE1103E/1K 数据手册

 浏览型号AFE1103E/1K的Datasheet PDF文件第7页浏览型号AFE1103E/1K的Datasheet PDF文件第8页浏览型号AFE1103E/1K的Datasheet PDF文件第9页浏览型号AFE1103E/1K的Datasheet PDF文件第11页浏览型号AFE1103E/1K的Datasheet PDF文件第12页浏览型号AFE1103E/1K的Datasheet PDF文件第13页 
In most systems, it will be natural to derive PVDD from the  
AVDD supply. A 5to 10resistor should be used to  
connect PVDD to the analog supply. This resistor in combi-  
nation with the 10µF capacitor form a lowpass filter—  
keeping glitches on AVDD from affecting PVDD. Ideally,  
PVDD would originate from the analog supply (via the  
resistor) near the power connector for the printed circuit  
board. Likewise, PGND should connect to a large PCB trace  
or small ground plane which returns to the power supply  
connector underneath the PVDD supply path. The PGND  
“ground plane” should also extend underneath PLLIN and  
PLLOUT (pins 47 and 48).  
LAYOUT  
The analog front end of an HDSL system has a number of  
conflicting requirements. It must accept and deliver digital  
outputs at fairly high rates of speed, phase-lock to a high-  
speed digital clock, and convert the line input to a high-  
precision (14-bit) digital output. Thus, there are really three  
sections of the AFE1103: the digital section, the phase-  
locked loop, and the analog section.  
The power supply for the digital section of the AFE1103 can  
range from 3.3V to 5V. This supply should be decoupled to  
digital ground with a ceramic 0.1µF capacitor placed as  
close to DGND (pin 12) and DVDD (pin 13) as possible.  
Ideally, both a digital power supply plane and a digital  
ground plane should run up to and underneath the digital  
pins of the AFE11103 (pins 3 through 26). However, DVDD  
may be supplied by a wide printed circuit board (PCB) trace.  
A digital ground plane underneath all digital pins is strongly  
recommended.  
The remaining portion of the AFE1103 should be considered  
analog. All AGND pins should be connected directly to a  
common analog ground plane and all AVDD pins should be  
connected to an analog 5V power plane. Both of these planes  
should have a low impedance path to the power supply.  
Ideally, all ground planes and traces and all power planes  
and traces should return to the power supply connector  
before being connected together (if necessary). Each ground  
and power pair should be routed over each other, should not  
overlap any portion of another pair, and the pairs should be  
separated by a distance of at least 0.25 inch (6mm). One  
exception is that the digital and analog ground planes should  
be connected together underneath the AFE1103 by a small  
trace.  
The phase-locked loop is powered from PVDD (pin 2) and its  
ground is referenced to PGND (pin 1). Note that PVDD must  
be in the 4.75V to 5.25V range. This portion of the AFE1103  
should be decoupled with both a 10µF Tantalum capacitor  
and a 0.1µF ceramic capacitor. The ceramic capacitor should  
be placed as close to the AFE1103 as possible. The place-  
ment of the Tantalum capacitor is not as critical, but should  
be close. In each case, the capacitor should be connected  
between PVDD and PGND.  
®
AFE1103  
10  

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