Datasheet > AFBR-775BHZ

AFBR-775BHZ

更新时间： 2022-02-26 10:40:01

品牌	Logo	应用领域
安华高科 - AVAGO		/
页数	文件大小	规格书
48页	978K
描述
Pluggable, Parallel-Fiber-Optics

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数据手册

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AFBR-775BHZ 数据手册

resumes. All interrupts can be masked and ﬂags are reset

upon reading the appropriate ﬂag register. The elec-

trical output will squelch for loss of input signal (unless

squelch is disabled) and channel de-activation through

TWS interface. Status and alarm information are available

via the TWS interface. The interrupt signal (selectable via

the TWS interface as a pulse or static level) is provided to

inform hosts of an assertion of an alarm and/or LOS.

Transmitter Input Equalization

Transmitter inputs can be programmed for one of several

levels of equalization. See Figure 4. The default case

provides a ﬂat gain-frequency response in the inputs.

Diﬀerent levels of compensation can be selected to

equalize skin-eﬀect losses across the host circuit board.

See Tx Memory Map 01h Upper Page section addresses

228 - 233 for programming details.

High Speed Signal Interface

No Equalization

Figure 3 shows the interface between an ASIC/SerDes and

the ﬁber optics modules. For simplicity, only one channel

is shown. As shown in the Figure 3, the compliance

points are on the host board side of the electrical connec-

tors. Sets of s-parameters are deﬁned for the transmit-

ter and receiver interfaces. The transmitter and receiver

are designed, when operating within Recommended

Operating Conditions, to provide a robust eye-opening at

the receiver outputs. See the Recommended Operating

Conditions and the Receiver Electrical Characteristics for

details.

Maximum Equalization

Frequency

Figure 4. Input Equalization

Unused inputs and outputs should be terminated with

100 Ω diﬀerential loads.

The transmitter inputs support a wide common mode

range and DC blocking capacitors may not be needed –

none are shown in Figure 3. Depending on the common

mode range tolerance of the ASIC/SerDes inputs, DC

blocking capacitors may be required in series with the

receiver. Diﬀerential impedances are nominally 100 Ω.

The common mode output impedance for the receiver is

nominally 25 Ω while the nominal common mode input

impedance of the transmitter is 25 Ω.

FO Rx Electrical Interface

ASIC/SerDes

C AC

S DD22

S CC22

S DC22

50 Ω

C AC

FO Rx (1 of 12 Lanes)

Host Board Electrical Interface

- Compliance Points -

50 Ω

S DD11

S CC11

S CD11

FO Tx (1 of 12 Lanes)

FO Tx Electrical Interface

Figure 3. Application Reference Diagram

1 234 5 6 7...48

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