Receiver Section
Application Support
The receiver section includes the Receiver Optical Sub-
Assembly (ROSA) and the amplification/quantization
circuitry. The ROSA, containing a PIN photodiode and
custom transimpedance amplifier, is located at the
optical interface and mates with the LC optical connec-
tor. The ROSA output is fed to a custom IC that provides
post-amplification and quantization.
An Evaluation Kit and Reference Designs are available to
assist in evaluation of the AFBR-57R5AEZ. Please contact
your local Field Sales representative for availability and
ordering details.
Caution
There are no user serviceable parts nor maintenance
requirements for the AFBR-57R5AEZ. All mechanical
adjustments are made at the factory prior to shipment.
Tampering with, modifying, misusing or improperly han-
dling the AFBR-57R5AEZ will void the product warranty.
It may also result in improper operation and possibly
overstress the laser source. Performance degradation
or device failure may result. Connection of the AFBR-
57R5AEZ to a light source not compliant with ANSI FC-PI
or IEEE 802.3 specifications, operating above maximum
operating conditions or in a manner inconsistent with
it’s design and function may result in exposure to haz-
ardous light radiation and may constitute an act of
modifying or manufacturing a laser product. Persons
performing such an act are required by law to re-certify
and re-identify the laser product under the provisions of
U.S. 21 CFR (Subchapter J) and TUV.
Receiver Loss of Signal (Rx_LOS)
The post-amplification IC also includes transition detec-
tion circuitry which monitors the ac level of incoming
optical signals and provides a TTL/CMOS compatible
status signal to the host (pin 8). An adequate optical
input results in a low Rx_LOS output while a high Rx_LOS
output indicates an unusable optical input. The Rx_LOS
thresholds are factory set so that a high output indicates
a definite optical fault has occurred. Rx_LOS can also be
monitored via the two-wire serial interface (address A2h,
byte 110, bit 1).
Functional Data I/O
The AFBR-57R5AEZ interfaces with the host circuit board
through twenty I/O pins (SFP electrical connector) iden-
tified by function in Table 2. The board layout for this in-
terface is depicted in Figure 6.
Ordering Information
Please contact your local field sales engineer or one of
Avago Technologies franchised distributors for order-
ing information. For technical information, please visit
Avago Technologies’ WEB page at www.Avago.com or
contact Avago Technologies Semicon-ductor Products
Customer Response Center at 1-800-235-0312. For infor-
mation related to SFF Committee documentation visit
www.sffcommittee.org.
The AFBR-57R5AEZ high speed transmit and receive in-
terfaces require SFP MSA compliant signal lines on the
host board. To simplify board requirements, biasing re-
sistors and ac coupling capacitors are incorporated into
the SFP transceiver module (per SFF-8074i) and hence
are not required on the host board. The Tx_Disable,
Tx_Fault, and Rx_LOS lines require TTL lines on the host
board (per SFF-8074i) if used. If an application chooses
not to take advantage of the functionality of these pins,
care must be taken to ground Tx_Disable (for normal op-
eration).
Figure 2 depicts the recommended interface circuit to
link the AFBR-57R5AEZ to supporting physical layer ICs.
Timing for MSA compliant control signals implemented
in the transceiver are listed in Figure 4.
4
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