Datasheet > AFBR-57F5PZ

AFBR-57F5PZ

更新时间： 2024-02-15 00:01:37

品牌	Logo	应用领域
安华高科 - AVAGO		通信放大器光纤
页数	文件大小	规格书
22页	517K
描述
Low Voltage (3.3V) Fibre Channel Optical Transceiver

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AFBR-57F5PZ 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8517.62.00.50	风险等级：	1.41
Is Samacsys：	N	主体宽度：	13.6 mm
主体高度：	8.6 mm	内置特性：	AMPLIFIER
通信标准：	GR-1089	连接类型：	LC CONNECTOR
数据速率（接收）：	14025 Mbps	数据速率（发送）：	14025 Mbps
发射极/检测器类型：	LASER	光纤设备类型：	TRANSCEIVER
光纤类型：	50/125, MMF	JESD-609代码：	e4
安装特点：	PANEL MOUNT	最高工作温度：	70 °C
最低工作温度：		最大工作波长：	860 nm
最小工作波长：	840 nm	标称工作波长：	850 nm
标称光功率输出：	0.16 mW	最小回损：	12 dB
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	NO
端子面层：	Gold (Au)	Base Number Matches：	1

AFBR-57F5PZ 数据手册

OPTICAL INTERFACE

LIGHT FROM FIBER

ELECTRICAL INTERFACE

RD+ (RECEIVE DATA)

RECEIVER

RD- (RECEIVE DATA)

Rx LOSS OF SIGNAL

Rx RATE SELECT RS(0)

Rx Vout &

Emphasis

CDR

AMPLIFICATION

& QUANTIZATION

PHOTO-DETECTOR

MOD-DEF2 (SDA)

µController

MOD-DEF1 (SCL)

MOD-DEF0

TRANSMITTER

TX_DISABLE

TD+ (TRANSMIT DATA)

LASER

DRIVER &

SAFETY

CDR

TD- (TRANSMIT DATA)

TX_FAULT

LIGHT TO FIBER

VCSEL

Equalization

CIRCUITRY

Tx RATE SELECT RS(1)

Figure 1. Transceiver functional diagram.

Transmitter Section

The transmitter section includes a Transmitter Optical

SubAssembly (TOSA), laser driver circuit, Clock and Data

Recovery circuit (CDR) and an electrical input stage with

variable equalization controls and electrical eye mea-

surement capability. The TOSA contains a 850nm Vertical

Cavity Surface Emitting Laser (VCSEL) light source with

integral light monitoring function and imaging optics to

assure eﬃcient optical coupling to the LC connector in-

terface. The TOSA is driven by a laser driver IC, which uses

the diﬀerential output from an integral Tx CDR stage to

modulate and regulate VCSEL optical power. As mandated

by FC-PI-5, the integral CDR cleans up any incoming jitter

accumulated from the host ASIC, PCB traces and SFP elec-

trical connector. Between the SFP electrical connector and

Tx CDR is a variable, i2c controlled, equalization circuit to

optimize SFP performance with non-ideal incoming elec-

trical waveforms. Note the Tx CDR is engaged only with

Tx_RATE=high (16GFC) and bypassed with Tx_RATE=low

(8G/4G).

tween successive assertions of this control signal. Tx_Dis-

able can also be asserted via the two-wire serial interface

(address A2h, byte 110, bit 6) and monitored (address

A2h, byte 110, bit 7).

The contents of A2h, byte 110, bit 6 are logic OR’d with

hardware Tx_Disable (pin 3) to control transmitter opera-

tion.

Transmit Fault (Tx_Fault)

A catastrophic laser fault will activate the transmitter sig-

nal, TX_FAULT, and disable the laser. This signal is an open

collector output (pull-up required on the host board). A

low signal indicates normal laser operation and a high

signal indicates a fault. The TX_FAULT will be latched high

when a laser fault occurs and is cleared by toggling the

TX_DISABLE input or power cycling the transceiver. The

transmitter fault condition can also be monitored via the

two-wire serial interface (address A2, byte 110, bit 2).

Eye Safety Circuit

Transmit Disable (Tx_Disable)

The AFBR-57F5PZ provides Class 1 (single fault tolerant)

eye safety by design and has been tested for compliance

with the requirements listed in Table 1. The eye safety

circuit continuously monitors the optical output power

level and will disable the transmitter upon detecting an

unsafe condition beyond the scope of Class 1 certiﬁcation.

Such unsafe conditions can be due to inputs from the host

board (Vcc ﬂuctuation, unbalanced code) or a fault within

the transceiver.

The AFBR-57F5PZ accepts a TTL and CMOS compatible

transmit disable control signal input (pin 3) which shuts

down the transmitter optical output. A high signal im-

plements this function while a low signal allows normal

transceiver operation. In the event of a fault (e.g. eye safe-

ty circuit activated), cycling this control signal resets the

module as depicted in Figure 4. An internal pull up resistor

disables the transceiver transmitter until the host pulls the

input low. Host systems should allow a 10 ms interval be-

1 234 5 6 7...22

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