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ADUM7440CRQZ

更新时间: 2024-01-08 21:38:28
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 425K
描述
1 kV RMS Quad-Channel Digital Isolators

ADUM7440CRQZ 数据手册

 浏览型号ADUM7440CRQZ的Datasheet PDF文件第1页浏览型号ADUM7440CRQZ的Datasheet PDF文件第2页浏览型号ADUM7440CRQZ的Datasheet PDF文件第4页浏览型号ADUM7440CRQZ的Datasheet PDF文件第5页浏览型号ADUM7440CRQZ的Datasheet PDF文件第6页浏览型号ADUM7440CRQZ的Datasheet PDF文件第7页 
ADuM7440/ADuM7441/ADuM7442  
SPECIFICATIONS  
ELECTRICAL CHARACTERISTICS—5 V OPERATION  
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended  
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications  
are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.  
Table 1.  
A Grade  
Typ  
C Grade  
Typ  
Parameter  
Symbol  
Min  
Max  
Min  
27  
Max  
Unit  
Test Conditions  
SWITCHING SPECIFICATIONS  
Data Rate  
Propagation Delay  
Pulse Width Distortion  
Change vs. Temperature  
Pulse Width  
Propagation Delay Skew  
Channel Matching  
Codirectional  
1
75  
25  
25  
50  
5
Mbps  
ns  
ns  
ps/°C  
ns  
ns  
Within PWD limit  
50% input to 50% output  
|tPLH − tPHL|  
tPHL, tPLH  
PWD  
50  
10  
5
40  
2
3
PW  
tPSK  
250  
40  
Within PWD limit  
Between any two units  
40  
25  
tPSKCD  
tPSKOD  
40  
40  
2
3
2
4
6
ns  
ns  
ns  
Opposing-Direction  
Jitter  
2
7
Codirectional channel matchin  
g
is the  
absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel matching is th  
e
absolute value  
of the  
difference in propagation delays between any two channels with inputs on opposin  
g
sides of the isolation barrier.  
Table 2.  
1 Mbps—A, C Grades  
25 Mbps—C Grade  
Parameter  
Symbol  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
Test Conditions  
SUPPLY CURRENT  
ADuM7440  
IDD1  
IDD2  
IDD1  
IDD2  
IDD1  
IDD2  
4.3  
2.5  
4.1  
3.6  
3.2  
3.2  
5.4  
3.6  
4.9  
4.7  
4.0  
4.0  
28  
6.0  
18  
8.5  
15  
12  
35  
11  
26  
14  
20  
17  
mA  
mA  
mA  
mA  
mA  
mA  
ADuM7441  
ADuM7442  
Table 3. For All Models  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions  
DC SPECIFICATIONS  
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
VIH  
VIL  
VOH  
0.7 VDDx  
V
V
V
V
0.3 VDDx  
VDDx − 0.1  
5.0  
4.8  
IOx = −20 μA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
VDDx − 0.4  
Logic Low Output Voltages  
VOL  
II  
0.0  
0.2  
+0.01  
0.1  
0.4  
+10  
V
V
μA  
IOx = 20 μA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
0 V ≤ VI x ≤ VDDx  
Input Current per Channel  
Supply Current per Channel  
Quiescent Input Supply Current  
Quiescent Output Supply Current  
Dynamic Input Supply Current  
Dynamic Output Supply Current  
AC SPECIFICATIONS  
−10  
IDDI(Q)  
IDDO(Q)  
IDDI(D)  
IDDO(D)  
0.76  
0.57  
0.26  
0.05  
0.95  
0.73  
mA  
mA  
mA/Mbps  
mA/Mbps  
Output Rise/Fall Time  
Common-Mode Transient Immunity1  
tR/tF  
|CM|  
2.0  
25  
ns  
kV/μs  
10% to 90%  
VIx = VDDx, VCM = 1000 V,  
15  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.2  
Mbps  
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both  
rising and falling common-mode voltage edges.  
Rev. 0 | Page 3 of 20  
 

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