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ADUM5403CRWZ1 PDF预览

ADUM5403CRWZ1

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
24页 591K
描述
Quad-Channel Isolators with Integrated DC-to-DC Converter

ADUM5403CRWZ1 数据手册

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ADuM5401/ADuM5402/ADuM5403/ADuM5404  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
ADuM5401CRWZ/ADuM5402CRWZ/  
ADuM5403CRWZ/ADuM5404CRWZ  
Minimum Pulse Width  
Maximum Data Rate  
Propagation Delay  
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
PW  
40  
ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
25  
tPHL, tPLH  
PWD  
45  
5
60  
6
|
ns  
ps/°C  
ns  
ns  
Propagation Delay Skew  
Channel-to-Channel Matching,  
Codirectional Channels  
tPSK  
tPSKCD  
45  
6
Channel-to-Channel Matching,  
Opposing Directional Channels  
Output Rise/Fall Time (10% to 90%)  
Common-Mode Transient Immunity  
at Logic High Output  
Common-Mode Transient Immunity  
at Logic Low Output  
tPSKOD  
15  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
VIx = VDD or VISO, VCM = 1000 V,  
transient magnitude = 800 V  
tR/tF  
|CMH|  
2.5  
35  
ns  
kV/μs  
25  
25  
|CML|  
fr  
35  
kV/μs  
Mbps  
VIx = 0 V, V = 1000 V,  
transient magnitude = 800 V  
Refresh Rate  
1.0  
1 The contributions of supply current values for all four channels are combined at identical data rates.  
2 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional  
current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as  
described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.  
3 The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent  
power consumed by the I/O channels as part of the internal power consumption.  
4 This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive  
load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum  
data rate.  
Rev. 0 | Page 6 of 24  
 

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