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ADUM5202CRWZ PDF预览

ADUM5202CRWZ

更新时间: 2024-02-26 14:27:21
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管接口集成电路
页数 文件大小 规格书
25页 1547K
描述
SPECIALTY ANALOG CIRCUIT, PDSO16, ROHS COMPLIANT, MS-013AA, SOIC-16

ADUM5202CRWZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknown风险等级:5.57
Is Samacsys:N其他特性:ALSO OPERATES WITH 5 VOLT SUPPLY
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:10.3 mm
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
座面最大高度:2.65 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.5 mm
Base Number Matches:1

ADUM5202CRWZ 数据手册

 浏览型号ADUM5202CRWZ的Datasheet PDF文件第16页浏览型号ADUM5202CRWZ的Datasheet PDF文件第17页浏览型号ADUM5202CRWZ的Datasheet PDF文件第18页浏览型号ADUM5202CRWZ的Datasheet PDF文件第20页浏览型号ADUM5202CRWZ的Datasheet PDF文件第21页浏览型号ADUM5202CRWZ的Datasheet PDF文件第22页 
ADuM5200/ADuM5201/ADuM5202  
APPLICATIONS INFORMATION  
The dc-to-dc converter section of the ADuM520x works on  
principles that are common to most power supplies. It has a  
secondary side controller architecture with isolated pulse-width  
modulation (PWM) feedback. VDD1 power is supplied to an  
oscillating circuit that switches current into a chip scale air core  
transformer. Power transferred to the secondary side is rectified  
and regulated to either 3.3 V or 5 V. The secondary (VISO) side  
controller regulates the output by creating a PWM control signal  
that is sent to the primary (VDD1) side by a dedicated iCoupler  
data channel. The PWM modulates the oscillator circuit to control  
the power being sent to the secondary side. Feedback allows for  
significantly higher power and efficiency.  
Note that the total lead length between the ends of the low ESR  
capacitor and the input power supply pin must not exceed 2 mm.  
Installing the bypass capacitor with traces more than 2 mm in  
length may result in data corruption. Consider bypassing between  
Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless both of the  
common ground pins are connected together close to the  
package.  
BYPASS < 2mm  
V
V
DD1  
ISO  
GND  
/V  
GND  
1
ISO  
V
V
V
/V  
IA OA  
OA IA  
V
/V  
IB OB  
/V  
OB IB  
RC  
NC  
IN  
The ADuM520x implements undervoltage lockout (UVLO) with  
hysteresis on the VDD1 power input. This feature ensures that the  
converter does not enter oscillation due to noisy input power or  
slow power on ramp rates.  
RC  
V
V
SEL  
SEL  
/NC  
E2  
V
/NC  
E1  
GND  
GND  
ISO  
1
Figure 21. Recommended PCB Layout  
A minimum load current of 10 mA is recommended to ensure  
optimum load regulation. Smaller loads can generate excess noise on  
chip due to short or erratic PWM pulses. Excess noise generated  
this way can cause data corruption in some circumstances.  
In applications involving high common-mode transients, ensure  
that board coupling across the isolation barrier is minimized.  
Furthermore, design the board layout such that any coupling  
that does occur equally affects all pins on a given component  
side. Failure to ensure this can cause differential voltages  
between pins exceeding the absolute maximum ratings for the  
device (specified in Table 8) thereby leading to latch-up and/or  
permanent damage.  
The ADuM520x can accept an external regulation control signal  
(RCIN) that can be connected to other isoPower devices. This  
allows a single regulator to control multiple power modules  
without contention. When accepting control from a master  
power module, the VISO pins can be connected together adding  
their power. Because there is only one feedback control path, the  
supplies work together seamlessly. The ADuM520x can only  
regulate itself or accept regulation (slave device) from another  
device in this product line; it cannot provide a regulation signal  
to other devices.  
The ADuM520x is a power device that dissipates approximately  
1 W of power when fully loaded and running at maximum speed.  
Because it is not possible to apply a heat sink to an isolation  
device, the device primarily depends on heat dissipation into  
the PCB through the GND pins. If the device is used at high  
ambient temperatures, provide a thermal path from the GND  
pins to the PCB ground plane. The board layout in Figure 21  
shows enlarged pads for Pin 2, Pin 8, Pin 9, and Pin 15. Multiple  
vias should be implemented from the pad to the ground plane  
to significantly reduce the temperature inside the chip. The  
dimensions of the expanded pads are at the discretion of the  
designer and depend on the available board space.  
PCB LAYOUT  
The ADuM520x digital isolators with 0.5 W isoPower integrated  
dc-to-dc converters require no external interface circuitry for the  
logic interfaces. Power supply bypassing is required at the input and  
output supply pins (see Figure 21). Note that low ESR bypass  
capacitors are required between Pin 1 and Pin 2 and between Pin  
15 and Pin 16, as close to the chip pads as possible.  
EMI CONSIDERATIONS  
The dc-to-dc converter section of the ADuM520x components  
must operate at a very high frequency to allow efficient power  
transfer through the small transformers. This creates high  
frequency currents that can propagate in circuit board ground  
and power planes, causing edge emissions and dipole radiation  
between the primary and secondary ground planes. Grounded  
enclosures are recommended for applications that use these  
devices. If grounded enclosures are not possible, follow good RF  
design practices in layout of the PCB. See www.analog.com for the  
most current PCB layout recommendations specifically for the  
ADuM520x.  
The power supply section of the ADuM520x uses a 180 MHz  
oscillator frequency to efficiently pass power through its chip  
scale transformers. In addition, normal operation of the data  
section of the iCoupler introduces switching transients on the  
power supply pins. Bypass capacitors are required for several  
operating frequencies. Noise suppression requires a low induc-  
tance, high frequency capacitor, whereas ripple suppression and  
proper regulation require a large value capacitor. These are most  
conveniently connected between Pin 1 and Pin 2 for VDD1 and  
between Pin 15 and Pin 16 for VISO. To suppress noise and reduce  
ripple, a parallel combination of at least two capacitors is required.  
The recommended capacitor values are 0.1 μF and 10 μF for VDD1  
.
The smaller capacitor must have a low ESR; for example, use of a  
ceramic capacitor is advised.  
Rev. 0 | Page 18 of 24  
 
 
 

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