Preliminary Technical Data
ADuM2400/ADuM2401/ADuM2402
Parameter
Symbol Min
Typ Max Unit
Test Conditions
SWITCHING SPECIFICATIONS
ADuM240xARW
Minimum Pulsewidth3
Maximum Data Rate4
PW
1000 ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
65
100
40
ns
ns
ns
ns
5
Pulsewidth Distortion, |tPLH-tPHL
|
Propagation Delay Skew6
Channel-to-Channel Matching7
ADuM240xBRW
50
tPSKCD/OD
50
Minimum Pulsewidth3
Maximum Data Rate4
Propagation Delay5
Pulsewidth Distortion, |tPLH – tPHL
Change Versus Temperature
Propagation Delay Skew6
PW
100
ns
Mbps
ns
ns
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
20
tPHL, tPLH
PWD
32
5
50
3
5
|
tPSK
tPSKCD
15
3
Channel-to-Channel Matching, Co-Directional
Channels7
ns
Channel-to-Channel Matching, Opposing-Directional
Channels7
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
ADuM240xCRW
Minimum Pulsewidth3
Maximum Data Rate4
PW
8.3
120
27
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
18
Propagation Delay5
tPHL, tPLH
PWD
32
2
5
Pulsewidth Distortion, |tPLH – tPHL
Change Versus Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Co-Directional
Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
10
2
Channel-to-Channel Matching, Opposing-Directional
Channels7
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10%–90%)
Common-Mode Transient Immunity at Logic High
Output8
t
PHZ, tPLH
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/DD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
tPZH, tPZL
tR/tF
|CMH|
2.5
35
ns
kV/µs
25
25
Common-Mode Transient Immunity at Logic Low
Output8
|CML|
35
kV/µs
Refresh Rate
fr
1.2
0.19
0.05
Mbps
mA/Mbps
mA/Mbps
Input Dynamic Supply Current, per Channel9
IDDI(D)
IDDO(D)
Output Dynamic Supply Current, per Channel9
See Notes on next page.
Rev. PrD | Page 3 of 23