ADuM2250/ADuM2251
AC Specifications
All voltages are relative to their respective ground. All minimum/maximum specifications apply over the entire recommended operating
range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 5 V, unless otherwise noted. See Figure 3
for a timing test diagram.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
MAXIMUM FREQUENCY
OUTPUT FALL TIME
5 V Operation
1000
kHz
4.5 V ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = 40 pF,
R1 = 1.6 kΩ, CL2 = 400 pF, R2 = 180 Ω
Side 1 Output (0.9 VDD1 to 0.9 V)
Side 2 Output (0.9 VDD2 to 0.1 VDD2
tf1
tf2
13
32
26
52
120
120
ns
ns
)
3 V Operation
3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = 40 pF,
R1 = 1.0 kΩ, CL2 = 400 pF, R2 = 120 Ω
Side 1 Output (0.9 VDD1 to 0.9 V)
Side 2 Output (0.9 VDD2 to 0.1 VDD2
PROPAGATION DELAY
tf1
tf2
13
32
32
61
120
120
ns
ns
)
5 V Operation
4.5 V ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = CL2 = 0 pF,
R1 = 1.6 kΩ, R2 = 180 Ω
Side 1 to Side 2, Rising Edge1
Side 1 to Side 2, Falling Edge2
Side 2 to Side 1, Rising Edge3
Side 2 to Side 1, Falling Edge4
3 V Operation
tPLH12
tPHL12
tPLH21
tPHL21
95
162
31
130
275
70
ns
ns
ns
ns
85
155
3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = CL2 = 0 pF,
R1 = 1.0 kΩ, R2 = 120 Ω
Side 1 to Side 2, Rising Edge1
Side 1 to Side 2, Falling Edge2
Side 2 to Side 1, Rising Edge3
Side 2 to Side 1, Falling Edge4
PULSE-WIDTH DISTORTION
5 V Operation
tPLH12
tPHL12
tPLH21
tPHL21
82
196
32
125
340
75
ns
ns
ns
ns
110
210
4.5 V ≤ VDD1, VDD2 ≤ 5.5 V, CL1 = CL2 = 0 pF,
R1 = 1.6 kΩ, R2 = 180 Ω
Side 1 -to Side 2, |tPLH12 − tPHL12
|
PWD12
PWD21
67
54
145
85
ns
ns
Side 2 to Side 1, |tPLH21 − tPHL21
3 V Operation
|
3.0 V ≤ VDD1, VDD2 ≤ 3.6 V, CL1 = CL2 = 0 pF,
R1 = 1.0 kΩ, R2 = 120 Ω
Side 1 to Side 2, |tPLH12 − tPHL12
Side 2 to Side 1, |tPLH21 − tPHL21
|
|
PWD12
PWD21
114
77
215
135
ns
ns
COMMON-MODE TRANSIENT IMMUNITY5
|CMH|, |CML|
25
35
kV/μs
1 tPLH12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 VDD2
2 tPHL12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V.
3 tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 VDD1
4 tPHL21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V.
.
.
5 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
Rev. 0 | Page 4 of 16