5秒后页面跳转
ADuM1300WSRWZ PDF预览

ADuM1300WSRWZ

更新时间: 2024-01-06 22:30:08
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
32页 453K
描述
Triple-Channel Digital Isolators

ADuM1300WSRWZ 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP16,.4针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8543.70.99.60风险等级:5.81
接口集成电路类型:INTERFACE CIRCUIT接口标准:EIA-232; EIA-422; EIA-485
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:10.3 mm湿度敏感等级:1
功能数量:3端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:Not Qualified筛选级别:AEC-Q100
座面最大高度:2.65 mm最大供电电压:5.5 V
最小供电电压:3 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mm

ADuM1300WSRWZ 数据手册

 浏览型号ADuM1300WSRWZ的Datasheet PDF文件第2页浏览型号ADuM1300WSRWZ的Datasheet PDF文件第3页浏览型号ADuM1300WSRWZ的Datasheet PDF文件第4页浏览型号ADuM1300WSRWZ的Datasheet PDF文件第6页浏览型号ADuM1300WSRWZ的Datasheet PDF文件第7页浏览型号ADuM1300WSRWZ的Datasheet PDF文件第8页 
Data Sheet  
ADuM1300/ADuM1301  
Parameter  
Symbol  
Min  
Typ Max Unit  
Test Conditions  
ADuM130xBRW  
Minimum Pulse Width2  
Maximum Data Rate3  
Propagation Delay4  
PW  
100 ns  
CL = 15 pF, CMOS signal levels  
10  
20  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
tPHL, tPLH  
PWD  
32  
5
50  
3
4
ns  
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew5  
|
ps/°C  
ns  
tPSK  
15  
3
Channel-to-Channel Matching, Codirectional  
Channels6  
tPSKCD  
ns  
Channel-to-Channel Matching, Opposing-  
Directional Channels6  
tPSKOD  
6
ns  
CL = 15 pF, CMOS signal levels  
ADuM130xCRW  
Minimum Pulse Width2  
Maximum Data Rate3  
Propagation Delay4  
PW  
8.3  
120  
27  
0.5  
3
11.1 ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
90  
18  
tPHL, tPLH  
PWD  
32  
2
4
ns  
Pulse Width Distortion, |tPLH − tPHL  
|
Change vs. Temperature  
Propagation Delay Skew5  
ps/°C  
ns  
tPSK  
10  
2
Channel-to-Channel Matching, Codirectional  
Channels6  
tPSKCD  
ns  
Channel-to-Channel Matching, Opposing-  
Directional Channels6  
tPSKOD  
5
ns  
CL = 15 pF, CMOS signal levels  
For All Models  
Output Disable Propagation Delay (High/Low  
to High Impedance)  
Output Enable Propagation Delay (High  
Impedance to High/Low)  
Output Rise/Fall Time (10% to 90%)  
Common-Mode Transient Immunity at Logic  
High Output7  
tPHZ, tPLH  
tPZH, tPZL  
6
6
8
8
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
VIx = VDD1 or VDD2, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, VCM = 1000 V,  
tR/tF  
|CMH|  
2.5  
35  
ns  
kV/μs  
25  
25  
Common-Mode Transient Immunity at Logic  
Low Output7  
|CML|  
35  
kV/μs  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.2  
Mbps  
Input Dynamic Supply Current per Channel8  
Output Dynamic Supply Current per Channel8  
IDDI (D)  
IDDO (D)  
0.19  
0.05  
mA/Mbps  
mA/Mbps  
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load  
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.  
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through  
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.  
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.  
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.  
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is  
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.  
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load  
within the recommended operating conditions.  
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of  
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with  
inputs on opposing sides of the isolation barrier.  
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate  
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient  
magnitude is the range over which the common mode is slewed.  
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information  
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current  
for a given data rate.  
Rev. I | Page 5 of 32  
 
 
 
 
 
 
 
 

与ADuM1300WSRWZ相关器件

型号 品牌 描述 获取价格 数据表
ADUM1300WSRWZ35 ADI Interface Circuit

获取价格

ADUM1300WSRWZ35-RL ADI Interface Circuit

获取价格

ADUM1300WSRWZ53 ADI Interface Circuit

获取价格

ADUM1300WSRWZ53-RL ADI Interface Circuit

获取价格

ADUM1300WSRWZ55 ADI 暂无描述

获取价格

ADUM1300WSRWZ55-RL ADI Interface Circuit

获取价格