ADuM1210
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All
minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications
are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V. All voltages are relative to their respective ground.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel,
Quiescent
IDDI (Q)
mA
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current, per Channel,
Quiescent
0.50
0.26
0.6
0.35
mA
mA
mA
IDDO (Q)
5 V/3 V Operation
3 V/5 V Operation
0.11
0.19
0.20
0.25
mA
mA
Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
1.1
0.6
1.4
1.0
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.2
0.5
0.6
0.8
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
10 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (10)
4.3
2.2
5.5
3.4
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
0.7
1.3
+0.01
1.1
2.0
+10
mA
mA
μA
V
V
V
V
V
V
V
5 MHz logic signal frequency
5 MHz logic signal frequency
0 V ≤ VIA, VIB ≤ VDD1
Input Currents
IIA, IIB
VIH
VIL
−10
0.7 × VDD1
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.3 × VDD1
VOAH, VOBH VDD2 − 0.1 VDD2
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD2 − 0.5
VDD2 − 0.2
0.0
0.04
0.2
Logic Low Output Voltages
VOAL, VOBL
0.1
0.1
0.4
SWITCHING SPECIFICATIONS
Minimum Pulse Width2
Maximum Data Rate3
PW
100
ns
Mbps
ns
ns
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
15
Propagation Delay4
tPHL, tPLH
PWD
55
3
4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
|
5
tPSK
tPSKCD
22
3
ns
Channel-to-Channel Matching,
tPSKOD
tR/tF
22
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels6
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3.0
2.5
ns
ns
3 V/5 V Operation
Rev. C | Page 7 of 20