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ADUM1210

更新时间： 2024-01-31 12:15:26
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 387K
描述
Dual-Channel Digital Isolator

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ADUM1210 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.4
Is Samacsys：N接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.75 mm最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3.9 mm
Base Number Matches：1

ADUM1210 数据手册

 浏览型号ADUM1210的Datasheet PDF文件第1页浏览型号ADUM1210的Datasheet PDF文件第2页浏览型号ADUM1210的Datasheet PDF文件第4页浏览型号ADUM1210的Datasheet PDF文件第5页浏览型号ADUM1210的Datasheet PDF文件第6页浏览型号ADUM1210的Datasheet PDF文件第7页 
ADuM1210  
SPECIFICATIONS  
ELECTRICAL CHARACTERISTICS—5 V OPERATION  
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range,  
unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. All voltages are relative to their respective ground.  
Table 1.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions  
DC SPECIFICATIONS  
Input Supply Current, per Channel,  
Quiescent  
Output Supply Current, per Channel,  
Quiescent  
IDDI (Q)  
0.50  
0.19  
0.60  
0.25  
mA  
mA  
IDDO (Q)  
Total Supply Current, Two Channels1  
DC to 2 Mbps  
VDD1 Supply Current  
VDD2 Supply Current  
10 Mbps  
IDD1 (Q)  
IDD2 (Q)  
1.1  
0.5  
1.4  
0.8  
mA  
mA  
DC to 1 MHz logic signal frequency  
DC to 1 MHz logic signal frequency  
VDD1 Supply Current  
VDD2 Supply Current  
Input Currents  
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
IDD1 (10)  
IDD2 (10)  
IIA, IIB  
VIH  
4.3  
1.3  
5.5  
2.0  
mA  
mA  
μA  
V
V
V
V
V
V
V
5 MHz logic signal frequency  
5 MHz logic signal frequency  
0 V ≤ VIA, VIB ≤ VDD1  
−10  
0.7 × VDD1  
+0.01 +10  
VIL  
0.3 × VDD1  
VOAH, VOBH VDD2 − 0.1  
VDD2 − 0.5  
VOAL, VOBL  
5.0  
4.8  
0.0  
0.04  
0.2  
IOx = −20 μA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
IOx = 20 μA, VIx = VIxL  
IOx = 400 μA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
Logic Low Output Voltages  
0.1  
0.1  
0.4  
SWITCHING SPECIFICATIONS  
Minimum Pulse Width2  
Maximum Data Rate3  
PW  
100  
ns  
Mbps  
ns  
ns  
ps/°C  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
10  
20  
Propagation Delay4  
tPHL, tPLH  
PWD  
50  
3
4
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew5  
Channel-to-Channel Matching,  
Codirectional Channels6  
|
5
tPSK  
tPSKCD  
15  
3
ns  
Channel-to-Channel Matching,  
tPSKOD  
15  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
VIx = VDD1, VCM = 1000 V,  
transient magnitude = 800 V  
Opposing-Directional Channels6  
Output Rise/Fall Time (10% to 90%)  
tR/tF  
|CMH|  
2.5  
35  
ns  
kV/μs  
Common-Mode Transient Immunity  
at Logic High Output7  
Common-Mode Transient Immunity  
at Logic Low Output7  
25  
25  
|CML|  
35  
kV/μs  
VIx = 0 V, VCM = 1000 V,  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.2  
Mbps  
Input Dynamic Supply Current,  
per Channel8  
IDDI (D)  
0.19  
mA/Mbps  
Output Dynamic Supply Current,  
per Channel8  
IDDO (D)  
0.05  
mA/Mbps  
1 Supply current values are for both channels running at identical data rates. Output supply current values are specified with no output load present. The supply current  
associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through Figure 6 for  
information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 through Figure 8 for total VDD1 and VDD2 supply  
currents as a function of data rate.  
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.  
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.  
Rev. C | Page 3 of 20  
 
 
 
 
 
 
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