Datasheet > ADUC7128

ADUC7128

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		微控制器数据分配系统
页数	文件大小	规格书
92页	744K
描述
Precision Analog Microcontroller ARM7TDMI MCU with 12-bit ADC & DDS DAC

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ADUC7128 数据手册

Preliminary Technical Data

ADuC7128

Parameter

Flash/EE MEMORY^7,8

ADuC7128

Unit

Test Conditions/Comments

Endurance

Data Retention

1±,±±±

2±

Cycles min

Years min

T_J= 85°C

Digital Inputs

All digital inputs including XCLKI and XCLKO

Logic 1 Input Current

(leakage Current )

Logic ± Input Current

(leakage Current )

±1

µA max

µA typ

µA max

µA typ

µA max

_INH= V_DDor V_INH= 5V

±±.2

-ꢀ±

-4±

-12±

-8±

_INL= ±V, except TDI

V_INL= ±V, TDI Only

µA typ

Input Capacitance

Logic Inputs³

1±

pF typ

All Logic inputs including XCLKI and XCLKO

VINL, Input Low Voltage

VINH, Input High Voltage

Quadrature Encoder Inputs S1/S2/CLR

(Schmitt-Triggered Inputs)

V_T+

±.8

2.±

V max

V min

1.9

2.1

±.9

1.1

±.9

1.1

V min

V max

V min

V max

V min

V max

V_T-

V_T+-V_T-

Logic Outputs⁹

VOH, Output High Voltage

IOV_DD– 4±±mV

±.4

V min

V max

I_SOURCE= 1.ꢀmA

I_SINK= 1.ꢀmA

VOL, Output Low Voltage

CRYSTAL INPUTS XCLKI and XCLKO

Logic Inputs, XCLKI Only

VINL, Input Low Voltage

1.1

1.7

2±

VINH, Input High Voltage

XCLKI Input Capacitance

XCLKO Output Capacitance

MCU CLOCK RATE (PLL)

2±

8 programmable core clock selections within this

range.

32ꢀ.4

kHz min

MHz max

kHz typ

% max

(32.7ꢀ8kHz x 1275)/128

(32.7ꢀ8kHz x 1275)/1

41.7792±±

32.7ꢀ8

±3

INTERNAL OSCILLATOR

Tolerance

STARTUP TIME

At Power-On

Core Clock = 41.78 MHz

TBD

From Pause/Nap Mode

From Sleep Mode

TBD

From Stop Mode

Programmable Logic Array (PLA)

Pin Propagation Delay

ns typ

From input pin to output pin

Rev. PrA | Page 5 of 92

1 2 3 456 7 8...92

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