Datasheet > ADT7475ARQ

ADT7475ARQ

更新时间： 2024-01-12 00:28:03

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
75页	899K
描述
ADT7475ARQ

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技术参数
数据手册

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ADT7475ARQ 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.82
Base Number Matches：	1

ADT7475ARQ 数据手册

ADT7475

Preliminary Technical Data

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

High Level Output Current, I_OH

SMBUS DIGITAL INPUTS (SCL, SDA)

Input High Voltage, V_IH

Input Low Voltage, V_IL

0.1

1.0

µA

V_OUT= V_CC

2.0

0.4

Hysteresis

500

DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)

Input High Voltage, V_IH

2.0

3.6

0.8

Maximum input voltage

Minimum input voltage

Input Low Voltage, V_IL

−0.3

Hysteresis

0.5

V p-p

DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+

Input High Voltage, V_IH

0.75 ×

V_CC

Input Low Voltage, V_IL

DIGITAL INPUT CURRENT

Input High Current, I_IH

Input Low Current, I_IL

Input Capacitance, C_IN

SERIAL BUS TIMING

0.4

−1

µA

V_IN= V_CC

V_IN= 0

See Figure 2

Clock Frequency, f_SCLK

Glitch Immunity, t_SW

Bus Free Time, t_BUF

Start Setup Time, t_SU;STA

Start Hold Time, t_HD;STA

SCL Low Time, t_LOW

400

kHz

µs

4.7

4.0

4.7

4.0

SCL High Time, t_HIGH

1000

300

SCL, SDA Rise Time, t_r

SCL, SDA Fall Time, t_f

Data Setup Time, t_SU;DAT

Data Hold Time, t_HD;DAT

Detect Clock Low Timeout, t_TIMEOUT

250

300

Can be optionally disabled

t_R

t_F

t_LOW

t_{HD; STA}

SCL

t_HIGH

t_{SU; STA}

t_{SU; STO}

t_{HD; STA}

t_{HD; DAT}

t_{SU; DAT}

SDA

t_BUF

Figure 2. Serial Bus Timing Diagram

Positive Supply Voltage (V_CC)

Maximum Voltage on all open-drain

outputs

3.6 V

Absolute Maximum Ratings.

Voltage on Any Input or Output Pin

Input Current at Any Pin

Package Input Current

−0.3 V to +4.2 V

5 mA

20 mA

Table 2.

Parameter

Rating

Rev. PrC | Page 4 of 75

1 2 345 6 7...75

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