ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
GENERAL DESCRIPTION
The ADSP-BF52x processors are members of the Blackfin fam-
ily of products, incorporating the Analog Devices/Intel Micro
Signal Architecture (MSA). Blackfin® processors combine a
dual-MAC state-of-the-art signal processing engine, the advan-
tages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which is the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. This capability can result in a substantial reduc-
tion in power consumption, compared with just varying the
frequency of operation. This allows longer battery life for
portable appliances.
The ADSP-BF52x processors are completely code compatible
with other Blackfin processors. The ADSP-BF523/
ADSP-BF525/ADSP-BF527 processors offer performance up to
600 MHz. The ADSP-BF522/ADSP-BF524/ADSP-BF526 pro-
cessors offer performance up to 400 MHz and reduced static
power consumption. Differences with respect to peripheral
combinations are shown in Table 1.
Table 1. Processor Comparison
SYSTEM INTEGRATION
The ADSP-BF52x processors are highly integrated system-on-a-
chip solutions for the next generation of embedded network
connected applications. By combining industry-standard inter-
faces with a high performance signal processing core, cost-
effective applications can be developed quickly, without the
need for costly external components. The system peripherals
include an IEEE-compliant 802.3 10/100 Ethernet MAC, a USB
2.0 high speed OTG controller, a TWI controller, a NAND flash
controller, two UART ports, an SPI port, two serial ports
(SPORTs), eight general purpose 32-bit timers with PWM capa-
bility, a core timer, a real-time clock, a watchdog timer, a Host
DMA (HOSTDP) interface, and a parallel peripheral interface
(PPI).
Feature
Host DMA
1
–
–
–
1
2
2
1
8
1
1
1
1
1
1
–
–
1
2
2
1
8
1
1
1
1
1
1
1
–
1
2
2
1
8
1
1
1
1
1
–
–
1
1
2
2
1
8
1
1
1
1
1
1
–
1
1
2
2
1
8
1
1
1
1
1
1
1
1
1
2
2
1
8
1
1
1
1
USB
Ethernet MAC
Internal Voltage Regulator
TWI
SPORTs
UARTs
SPI
PROCESSOR PERIPHERALS
GP Timers
GP Counter
Watchdog Timers
RTC
The ADSP-BF52x processors contain a rich set of peripherals
connected to the core via several high bandwidth buses, provid-
ing flexibility in system configuration as well as excellent overall
system performance (see the block diagram on Page 1).
Parallel Peripheral Interface
GPIOs
These Blackfin processors contain dedicated network commu-
nication modules and high speed serial and parallel ports, an
interrupt controller for flexible management of interrupts from
the on-chip peripherals or external sources, and power manage-
ment control functions to tailor the performance and power
characteristics of the processor and system to many application
scenarios.
48 48 48 48 48 48
48K 48K 48K 48K 48K 48K
L1 Instruction SRAM
L1 Instruction SRAM/Cache 16K 16K 16K 16K 16K 16K
L1 Data SRAM
32K 32K 32K 32K 32K 32K
32K 32K 32K 32K 32K 32K
4K 4K 4K 4K 4K 4K
32K 32K 32K 32K 32K 32K
L1 Data SRAM/Cache
L1 Scratchpad
L3 Boot ROM
All of the peripherals, except for the general-purpose I/O, TWI,
real-time clock, and timers, are supported by a flexible DMA
structure. There are also separate memory DMA channels dedi-
cated to data transfers between the processor's various memory
spaces, including external SDRAM and asynchronous memory.
Multiple on-chip buses running at up to 133 MHz provide
enough bandwidth to keep the processor core running along
with activity on all of the on-chip and external peripherals.
Maximum Instruction Rate1
Maximum System Clock Speed
Package Options
400 MHz
100 MHz
600 MHz
133 MHz
289-Ball CSP_BGA
208-Ball CSP_BGA
1 Maximum instruction rate is not available with every possible SCLK selection.
The ADSP-BF523/ADSP-BF525/ADSP-BF527 processors
include an on-chip voltage regulator in support of the proces-
sor’s dynamic power management capability. The voltage
Rev. D
| Page 3 of 88 | July 2013
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