ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
power-down state. For additional information, refer to the
ADSP-218x DSP Hardware Reference, for detailed information
on this power-down feature.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL pin must be left unconnected.
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-218xL series, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories
(mode-selectable). Programmable wait state generation allows
the processor to connect easily to slow peripheral devices.
ADSP-218xL series members also provide four external inter-
rupts and two serial ports or six external interrupts and one
serial port. Host Memory Mode allows access to the full external
data bus, but limits addressing to a single address bit (A0).
Through the use of external hardware, additional system
peripherals can be added in this mode to generate and latch
address signals.
ADSP-218xL series members use an input clock with a fre-
quency equal to half the instruction rate; a 40 MHz input clock
yields a 12.5 ns processor cycle (which is equivalent to
80 MHz). Normally, instructions are executed in a single pro-
cessor cycle. All device timing is relative to the internal
instruction clock rate, which is indicated by the CLKOUT signal
when enabled.
Because ADSP-218xL series members include an on-chip oscil-
lator circuit, an external crystal may be used. The crystal should
be connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in Figure 3. Capacitor values are
dependent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. To provide an
adequate feedback path around the internal amplifier circuit,
place a resistor in parallel with the circuit, as shown in Figure 3.
Clock Signals
ADSP-218xL series members can be clocked by either a crystal
or a TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
nor operated below the specified frequency during normal oper-
ation. The only exception is while the processor is in the
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
FULL MEMORY MODE
ADSP-218xL
HOST MEMORY MODE
ADSP-218xL
OR
CRYSTAL
CLKIN
XTAL
FL0–2
CLKIN
OR
CRYSTAL
A13–0
14
XTAL
ADDR13–0
1
A0
D23–16
D15–8
A0–A21
FL0–2
BYTE
MEMORY
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
16
24
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
DATA23–8
DATA23–0
DATA
CS
BMS
BMS
MODE D/PF3
MODE C/PF2
MODE A/PF0
A10–0
D23–8
WR
RD
WR
RD
MODE D/PF3
MODE C/PF2
MODE A/PF0
MODE B/PF1
ADDR
I/O SPACE
(PERIPHERALS)
2048 LOCATIONS
MODE B/PF1
DATA
IOMS
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
CS
IOMS
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
A13–0
D23–0
SERIAL
DEVICE
OVERLAY
MEMORY
ADDR
DATA
SERIAL
DEVICE
TWO 8K
PM SEGMENTS
DR1 OR FI
PMS
DMS
CMS
PMS
DMS
CMS
SPORT0
SCLK0
RFS0
TFS0
DT0
TWO 8K
DM SEGMENTS
SPORT0
SCLK0
RFS0
TFS0
DT0
SERIAL
DEVICE
BR
BG
BGH
PWD
BR
BG
BGH
PWD
SERIAL
DEVICE
DR0
IDMA PORT
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
DR0
PWDACK
PWDACK
SYSTEM
INTERFACE
OR
µCONTROLLER
IAD15-0
16
NOTE: MODE D APPLIES TO THE ADSP-2187L PROCESSOR ONLY
Figure 2. Basic System Interface
Rev. C
|
Page 7 of 48
|
January 2008
5秒后页面跳转
NE5532P芯片资料：引脚说明、电气参数及替换型号推荐
解读MMBT5401数据手册：电气参数及替换型号推荐
深入解读BAV70数据手册：特性、电气参数及替换型号推荐
74HC595D芯片引脚图及功能、参数介绍、替代型号推荐
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
