ADSP-21xx
T he interrupt force and clear register, IFC, is a write-only
register that contains a force bit and a clear bit for each inter-
rupt (except for level-sensitive interrupts and the ADSP-2111
HIP interrupts—these cannot be forced or cleared in software).
SYSTEM INTERFACE
Figure 3 shows a typical system for the ADSP-2101, ADSP-
2115, or ADSP-2103, with two serial I/O devices, a boot
EPROM, and optional external program and data memory. A
total of 15K words of data memory and 16K words of program
memory is addressable for the ADSP-2101 and ADSP-2103. A
total of 14.5K words of data memory and 15K words of
program memory is addressable for the ADSP-2115.
When responding to an interrupt, the AST AT , MST AT , and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
T he status stack is seven levels deep (nine levels deep on the
ADSP-2111) to allow interrupt nesting. T he stack is automati-
cally popped when a return from the interrupt instruction is
executed.
Figure 4 shows a system diagram for the ADSP-2105, with one
serial I/O device, a boot EPROM, and optional external
program and data memory. A total of 14.5K words of data
memory and 15K words of program memory is addressable for
the ADSP-2105.
P in D efinitions
T able IV (on next page) shows pin definitions for the ADSP-
21xx processors. Any inputs not used must be tied to VDD
.
Figure 5 shows a system diagram for the ADSP-2111, with two
serial I/O devices, a host processor, a boot EPROM, and
optional external program and data memory. A total of 15K
words of data memory and 16K words of program memory is
addressable.
Table III. Interrupt Vector Addresses & P riority
AD SP -2105
Interrupt
Source
Interrupt
Vector Address
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
RESET Startup
IRQ2
SPORT 1 T ransmit or IRQ1
SPORT 1 Receive or IRQ0
T imer
0x0000
0x0004 (High Priority)
0x0010
0x0014
0x0018 (Low Priority)
T he ADSP-2101, ADSP-2103, ADSP-2115, and ADSP-2111
processors also provide either: one external interrupt (IRQ2)
and two serial ports (SPORT 0, SPORT 1), or three external
interrupts (IRQ2, IRQ1, IRQ0) and one serial port (SPORT 0).
T he ADSP-2105 provides either: one external interrupt (IRQ2)
and one serial port (SPORT 1), or three external interrupts
(IRQ2, IRQ1, IRQ0) with no serial port.
AD SP -2101/2103/2115/216x
Interrupt
Interrupt
Source
Vector Address
Clock Signals
T he ADSP-21xx processors’ CLKIN input may be driven by a
crystal or by a T T L-compatible external clock signal. T he
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
RESET Startup
IRQ2
0x0000
0x0004 (High Priority)
0x0008
0x000C
0x0010
SPORT 0 T ransmit
SPORT 0 Receive
SPORT 1 T ransmit or IRQ1
SPORT 1 Receive or IRQ0
T imer
If an external clock is used, it should be a T T L-compatible
signal running at the instruction rate. T he signal should be
connected to the processor’s CLKIN input; in this case, the
XT AL input must be left unconnected.
0x0014
0x0018 (Low Priority)
AD SP -2111
Interrupt
Source
Because the ADSP-21xx processors include an on-chip oscilla-
tor circuit, an external crystal may also be used. T he crystal
should be connected across the CLKIN and XT AL pins, with
two capacitors connected as shown in Figure 2. A parallel-
resonant, fundamental frequency, microprocessor-grade crystal
should be used.
Interrupt
Vector Address
RESET Startup
IRQ2
0x0000
0x0004 (High Priority)
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020 (Low Priority)
HIP Write from Host
HIP Read to Host
SPORT 0 T ransmit
SPORT 0 Receive
SPORT 1 T ransmit or IRQ1
SPORT 1 Receive or IRQ0
T imer
XTAL
ADSP-21xx
CLKIN
CLKOUT
Figure 2. External Crystal Connections
REV. B
–7–
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