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ADSP-21375KSZ-ENG PDF预览

ADSP-21375KSZ-ENG

更新时间: 2024-02-19 06:01:14
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
42页 1922K
描述
SHARC Processor

ADSP-21375KSZ-ENG 数据手册

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Preliminary Technical Data  
ADSP-21375  
TABLE OF CONTENTS  
Summary ................................................................1  
Key Features – Processor Core ..................................2  
Input/Output Features ............................................2  
General Description ..................................................4  
ADSP-21375 Family Core Architecture .......................4  
ADSP-21375 Memory .............................................5  
External Memory ...................................................5  
ADSP-21375 Input/Output Features ...........................7  
System Design .......................................................9  
Development Tools ................................................9  
Pin Function Descriptions ........................................ 12  
Data Modes ........................................................ 15  
Boot Modes ........................................................ 15  
Core Instruction Rate to CLKIN Ratio Modes ............. 15  
ADSP-21375 Specifications ....................................... 16  
Recommended Operating Conditions ....................... 16  
Electrical Characteristics ........................................ 16  
Absolute Maximum Ratings ................................... 17  
Maximum Power Dissipation ................................. 17  
ESD Sensitivity .................................................... 17  
Timing Specifications ........................................... 17  
Output Drive Currents .......................................... 39  
Test Conditions ................................................... 39  
Capacitive Loading ............................................... 39  
Thermal Characteristics ........................................ 40  
208-Lead MQFP Pinout ............................................ 41  
Package Dimensions ................................................ 42  
Ordering Guide ...................................................... 42  
REVISION HISTORY  
12/05—Revision changed from PrA to PrB.  
Modified Figure 1, Functional Block Diagram,..................1  
SDRAM bank address example in last paragraph of SDRAM  
Controller ...............................................................6  
Added Two Wire Interface Port (TWI) ..........................9  
Added TWI Controller Timing .................................. 37  
Rev. PrB  
| Page 3 of 42 | December 2005  

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