Preliminary Technical Data
ADSP-21368
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
sufficient registers to allow the creation of up to 32 circular buff-
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over-
head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21368 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
Single-Cycle Fetch of Instruction and Four Operands
ADSP-21368 MEMORY
The ADSP-21368 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1 on page 1). With the ADSP-21368’s separate pro-
gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.
The ADSP-21368 adds the following architectural features to
the SIMD SHARC family core.
On-Chip Memory
The ADSP-21368 contains two megabits of internal RAM and
six megabits of internal mask-programmable ROM. Each block
can be configured for different combinations of code and data
storage (see Table 2). Each memory block supports single-cycle,
independent accesses by the core processor and I/O processor.
The ADSP-21368 memory architecture, in combination with its
separate on-chip buses, allow two data transfers from the core
and one from the I/O processor, in a single cycle.
Instruction Cache
The ADSP-21368 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
The ADSP-21368’s, SRAM can be configured as a maximum of
64K words of 32-bit data, 128K words of 16-bit data, 42K words
of 48-bit instructions (or 40-bit data), or combinations of differ-
ent word sizes up to three megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-
ing-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21368’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21368 contain
Table 2. ADSP-21368 Internal Memory Space
IOP Registers 0x0000 0000 - 0003 FFFF
Long Word (64 bits)
ExtendedPrecisionNormalor Normal Word (32 bits)
Short Word (16 bits)
Instruction Word (48 bits)
BLOCK 0 ROM
BLOCK 0 ROM
BLOCK 0 ROM
BLOCK 0 ROM
0x0004 0000–0x0004 BFFF
0x0008 0000–0x0008 FFFF
0x0008 0000–0x0009 7FFF
0x0010 0000–0x0012 FFFF
Reserved
Reserved
Reserved
Reserved
0x0004 F000–0x0004 FFFF
0x0009 4000–0x0009 FFFF
0x0009 E0000–0x0009 FFFF
0x0013 C000–0x0013 FFFF
BLOCK 0 RAM
BLOCK 0 RAM
BLOCK 0 RAM
BLOCK 0 RAM
0x0004 C000–0x0004 EFFF
0x0009 0000–0x0009 3FFF
0x0009 8000–0x0009 DFFF
0x0013 0000–0x0013 BFFF
BLOCK 1 ROM
BLOCK 1 ROM
BLOCK 1 ROM
BLOCK 1 ROM
0x0005 0000–0x0005 BFFF
0x000A 0000–0x000A FFFF
0x000A 0000– 0x000B 7FFF
0x0014 0000–0x0016 FFFF
Rev. PrA
|
Page 5 of 48 | November 2004
5秒后页面跳转
TLP250光耦合器：资料手册参数分析
DA14580 低功耗蓝牙系统级芯片(SoC)：资料手册参数分析
INA226 高精度电流和功率监控器：资料手册参数分析
SI2302 N沟道MOSFET：资料手册参数分析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
