Datasheet > ADSP-21367KBPZ-X

ADSP-21367KBPZ-X

更新时间： 2024-02-23 11:24:37

品牌	Logo	应用领域
亚德诺 - ADI		时钟外围集成电路
页数	文件大小	规格书
60页	1360K
描述
IC 32-BIT, 55.55 MHz, OTHER DSP, PBGA256, LEAD FREE, MO-192BAL-2, SBGA-256, Digital Signal Processor

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ADSP-21367KBPZ-X 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LEAD FREE, MO-192BAL-2, SBGA-256	针数：	256
Reach Compliance Code：	compliant	ECCN代码：	3A991.A.2
HTS代码：	8542.31.00.01	风险等级：	5.72
其他特性：	ALSO REQUIRES 3.3V SUPPLY	地址总线宽度：	24
桶式移位器：	YES	位大小：	32
边界扫描：	YES	最大时钟频率：	55.55 MHz
外部数据总线宽度：	32	格式：	FLOATING POINT
内部总线架构：	MULTIPLE	JESD-30 代码：	S-PBGA-B256
长度：	27 mm	低功率模式：	NO
端子数量：	256	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	HLBGA	封装等效代码：	BGA256,20X20,50
封装形状：	SQUARE	封装形式：	GRID ARRAY, HEAT SINK/SLUG, LOW PROFILE
峰值回流温度（摄氏度）：	260	电源：	1.3,3.3 V
认证状态：	Not Qualified	RAM（字数）：	65536
座面最大高度：	1.7 mm	子类别：	Digital Signal Processors
最大供电电压：	1.365 V	最小供电电压：	1.235 V
标称供电电压：	1.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	27 mm	uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：	1

ADSP-21367KBPZ-X 数据手册

ADSP-21367/ADSP-21368/ADSP-21369

GENERAL DESCRIPTION

The ADSP-21367/ADSP-21368/ADSP-21369 SHARC^®proces-

sors are members of the SIMD SHARC family of DSPs that

feature Analog Devices’ Super Harvard Architecture. These pro-

cessors are source code-compatible with the ADSP-2126x and

ADSP-2116x DSPs as well as with first generation ADSP-2106x

SHARC processors in SISD (single-instruction, single-data)

mode. The processors are 32-bit/40-bit floating-point proces-

sors optimized for high performance automotive audio

applications with its large on-chip SRAM, mask programmable

ROM, multiple internal buses to eliminate I/O bottlenecks, and

an innovative digital applications interface (DAI).

Table 2. ADSP-2136x Family Features¹(Continued)

Feature

Serial Ports

IDP

Yes

DAI

Yes

As shown in the functional block diagram on Page 1, the

processors use two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. Fabricated in a state-of-the-art, high

speed, CMOS process, the ADSP-21367/ADSP-21368/

ADSP-21369 processors achieve an instruction cycle time of up

to 2.5 ns at 400 MHz. With its SIMD computational hardware,

the processors can perform 2.4 GFLOPS running at 400 MHz.

UART

DAI and DPI

S/PDIF Transceiver

AMI Interface Bus Width

SPI

Yes

32/16/8 bits

Table 1 shows performance benchmarks for these devices.

TWI

Yes

128 dB

SRC Performance

Package

Table 1. Processor Benchmarks (at 400 MHz)

256 Ball- 256 Ball- 256 Ball-

Speed

(at 400 MHz)

BGA,

208-Lead

LQFP_EP

BGA

BGA,

208-Lead

LQFP_EP

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, with reversal) 23.2 μs

FIR Filter (per tap)¹

IIR Filter (per biquad)¹

Matrix Multiply (pipelined)

[3×3] × [3×1]

1.25 ns

5.0 ns

¹W = Automotive grade product. See Automotive Products on Page 58 for more

information.

²Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,

DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass

management, delay, speaker equalization, graphic equalization, and more.

Decoder/post-processoralgorithmcombinationsupportvariesdependingupon

the chip version and the system configurations. Please visit www.analog.com for

complete information.

11.25 ns

20.0 ns

8.75 ns

13.5 ns

[4×4] × [4×1]

Divide (y/x)

Inverse Square Root

¹Assumes two files in multichannel SIMD mode.

The diagram on Page 1 shows the two clock domains that make

up the ADSP-21367/ADSP-21368/ADSP-21369 processors. The

core clock domain contains the following features.

• Two processing elements (PEx, PEy), each of which com-

prises an ALU, multiplier, shifter, and data register file

Table 2. ADSP-2136x Family Features¹

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting 2x64-bit data

transfers between memory and the core at every core pro-

cessor cycle

Feature

Frequency

400 MHz

• One periodic interval timer with pinout

• On-chip SRAM (2M bit)

• On-chip mask-programmable ROM (6M bit)

• JTAG test access port for emulation and boundary scan.

The JTAG provides software debug through user break-

points which allows flexible exception handling.

RAM

ROM²

2M bits

6M bits

Yes

Audio Decoders in ROM

Pulse-Width Modulation

S/PDIF

Yes

SDRAM Memory Bus Width

32/16 bits

Rev. E

| Page 3 of 60 | July 2009

1 234 5 6 7...60

中文翻译

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与ADSP-21367KBPZ-X相关器件

型号	品牌	获取价格	描述	数据表
ADSP-21367KSWZ-1A	ADI	获取价格	SHARC Processors
ADSP-21367KSWZ-2A	ADI	获取价格	SHARC Processors
ADSP-21367KSWZ-4A	ADI	获取价格	SHARC Processors
ADSP-21367KSWZ-5A	ADI	获取价格	SHARC Processors
ADSP-21367KSZ-1A	ADI	获取价格	SHARC Processors
ADSP-21367KSZ-ENG	ADI	获取价格	暂无描述
ADSP-21367KSZ-X	ADI	获取价格	IC 32-BIT, OTHER DSP, PQFP208, LEAD FREE, MS-029FA-1, MQFP-208, Digital Signal Processor
ADSP-21367SKBP-ENG	ADI	获取价格	SHARC Processor
ADSP-21367SKBPZENG	ADI	获取价格	SHARC Processor
ADSP-21367SKSZ-ENG	ADI	获取价格	SHARC Processor

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