ADSP-21365
Using the DM bus and PM buses, with one bus dedicated to
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.
TO PROCESSOR BUSES AND
SYSTEM MEMORY
IO DATA
BUS (32)
IO ADDRESS
BUS (18)
DMA Controller
GPIO FLAGS/IRQ/TIMEXP
The ADSP-21365’s on-chip DMA controllers allow data trans-
fers without processor intervention. The DMA controller
operates independently and invisibly to the processor core,
allowing DMA operations to occur while the core is simulta-
neously executing its program instructions. DMA transfers can
occur between the ADSP-21365’s internal memory and its serial
ports, the SPI-compatible (serial peripheral interface) ports, the
IDP (input data port), the parallel data acquisition port (PDAP)
or the parallel port. Twenty-five channels of DMA are available
on the processors—two for the SPI interface, 12 via the serial
ports, eight via the input data port, two for DTCP (or memory-
to-memory data transfer when DTCP is not used), and one via
the processor’s parallel port. Programs can be downloaded to
the processors using DMA transfers. Other DMA features
include interrupt generation upon completion of DMA trans-
fers, and DMA chaining for automatic linked DMA transfers.
4
3
DMA CONTROLLER
25 CHANNELS
CONTROL/GPIO
16
ADDRESS/DATA BUS/GPIO
PARALLEL PORT
PWM (16)
SPI PORT (1)
4
4
SPI PORT (1)
SERIAL PORTS (6)
INPUT
DATA PORTS (8)
20
Digital Audio Interface (DAI)
DTCP CIPHER
SPDIF (Rx/Tx)
The digital audio interface (DAI) provides the ability to connect
various peripherals to any of the DSP’s DAI pins (DAI_P20–1).
Programs make these connections using the signal routing unit
(SRU, shown in Figure 3).
SRC (8 CHANNELS)
PRECISION CLOCK
GENERATORS (2)
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI-
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.
3
TIMERS (3)
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
The DAI also includes six serial ports, an S/PDIF receiver/trans-
mitter, a DTCP cipher, a precision clock generator (PCG), eight
channels of asynchronous sample rate converters, an input data
port (IDP), an SPI port, six flag outputs and six flag inputs, and
three timers. The IDP provides an additional input path to the
ADSP-21365 core, configurable as either eight channels of I2S
serial data or as seven channels plus a single 20-bit wide syn-
chronous parallel data acquisition port. Each data channel has
its own DMA channel that is independent from the processor’s
serial ports.
Figure 3. ADSP-21365 I/O Processor and
Peripherals Block Diagram
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTS are enabled,
or six full duplex TDM streams of 128 channels per frame.
The serial ports operate at a maximum data rate of 50M bits/s.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig-
nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
For complete information on using the DAI, see the
ADSP-2136x SHARC Processor Hardware Reference.
Serial Ports
The ADSP-21365 features six synchronous serial ports that pro-
vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and a frame sync.
The data lines can be programmed to either transmit or receive
and each data line has a dedicated DMA channel.
Serial ports operate in four modes:
• Standard DSP serial mode
• Multichannel (TDM) mode
• I2S mode
• Left-justified sample pair mode
Rev. 0
|
Page 7 of 56
|
October 2005
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