Datasheet > ADS7881_14

ADS7881_14

更新时间： 2022-10-12 16:14:23

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
26页	335K
描述
4 MHz Sample Rate, 12-Bit Resolution High Speed Parallel Interface

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SLAS400 − SEPTEMBER 2003

SPECIFICATIONS Continued

= −40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, V = 2.5 V, f

= 4 MHz (unless otherwise noted)

ref

sample

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL REFERENCE OUTPUT

From 95% (+VA), with 1-µF storage

capacitor on REFOUT to AGND

Start-up time

120

2.53

msec

REF

Range

IOUT=0

2.47

2.5

µA

Source current

Line regulation

Drift

Static load

+VA = 4.75 V to 5.25 V

IOUT = 0

PPM/C

DIGITAL INPUT/OUTPUT

Logic family

CMOS

= 5 µA

−1

+ 0.3

0.8

−0.3

− 0.6

Logic level

= 2 TTL loads

0.4

Straight

Binary

Data format

POWER SUPPLY REQUIREMENTS

+VBD

Power supply voltage

+VA

2.7

3.3

5.25

4.75

Supply current, +VA, 4 MHz sample rate

Power dissipation, 4 MHz sample rate

NAP MODE

+VA = 5 V

110

Supply current, +VA

(7)

Power-up time

nsec

POWER DOWN

Supply current, +VA

2.5

µA

(8)

Power down time

From simulation results

µsec

1-µF Storage capacitor on REFOUT to

AGND

Power up time

msec

Invalid conversions after power up or reset

TEMPERATURE RANGE

Numbers

Operating free-air

−40

°C

(1)

Ideal input span; does not include gain or offset error.

This is endpoint INL, not best fit.

LSB means least significant bit.

Measured relative to actual measured reference.

Calculated on the first nine harmonics of the input frequency.

Can vary 20%.

(2)

(3)

(4)

(5)

(6)

(7)

(8)

Minimum acquisition time for first sampling after the end of nap state must be 60 nsec more than normal.

Time required to reach level of 2.5 µA.

1 2 345 6 7...26

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