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ADP3155JRU-REEL PDF预览

ADP3155JRU-REEL

更新时间: 2024-02-26 02:59:05
品牌 Logo 应用领域
亚德诺 - ADI 控制器
页数 文件大小 规格书
14页 202K
描述
IC SWITCHING CONTROLLER, PDSO20, TSSOP-20, Switching Regulator or Controller

ADP3155JRU-REEL 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:unknown风险等级:5.23
Is Samacsys:N模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制模式:CURRENT-MODE控制技术:CONSTANT OFF TIME
标称输入电压:12 VJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:6.5 mm
湿度敏感等级:NOT SPECIFIED功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):220
认证状态:COMMERCIAL座面最大高度:1.2 mm
表面贴装:YES切换器配置:PUSH-PULL
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

ADP3155JRU-REEL 数据手册

 浏览型号ADP3155JRU-REEL的Datasheet PDF文件第3页浏览型号ADP3155JRU-REEL的Datasheet PDF文件第4页浏览型号ADP3155JRU-REEL的Datasheet PDF文件第5页浏览型号ADP3155JRU-REEL的Datasheet PDF文件第7页浏览型号ADP3155JRU-REEL的Datasheet PDF文件第8页浏览型号ADP3155JRU-REEL的Datasheet PDF文件第9页 
ADP3155  
12V  
Table I. Output Voltage vs. VID Code  
VID0–  
VID4  
V
5-BIT CODE  
CC  
VID4 VID3 VID2 VID1 VID0 VOUT  
0.1F  
1F  
ADP3155  
SD  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.30  
DRIVE1  
CMP  
1.35  
1.40  
1.45  
1.50  
1.55  
1.60  
1.65  
1.70  
1.75  
1.80  
1.85  
1.90  
1.95  
2.00  
2.05  
DRIVE2  
1k⍀  
C
T
SENSE+  
SENSE–  
PGND  
4700pF  
AGND  
V
OUT  
OP27  
100k⍀  
1.2V  
0.1F  
Figure 13. Closed-Loop Test Circuit for Accuracy  
THEORY OF OPERATION  
The ADP3155 uses a current-mode, constant-off-time control  
technique to switch a pair of external N-channel MOSFETs in  
a synchronous buck topology. Constant off-time operation  
offers several performance advantages, including that no slope  
compensation is required for stable operation. A unique feature  
of the constant-off-time control technique is that since the off-  
time is fixed, the converter’s switching frequency is a function  
of the ratio of input voltage to output voltage. The fixed off-  
time is programmed by the value of an external capacitor con-  
nected to the CT pin. The on-time varies in such a way that a  
regulated output voltage is maintained as described below in the  
cycle-by-cycle operation. Under fixed operating conditions the  
on-time does not vary, and it varies only slightly as a function of  
load. This means that switching frequency is fairly constant in  
standard VRM applications. In order to maintain a ripple cur-  
rent in the inductor that is independent of the output voltage  
(which also helps control losses and simplify the inductor de-  
sign), the off-time is made proportional to the value of the out-  
put voltage. Normally, the output voltage is constant and,  
therefore, the off-time is constant as well.  
No CPU–Shutdown  
2.10  
2.20  
2.30  
2.40  
2.50  
2.60  
2.70  
2.80  
2.90  
3.00  
3.10  
3.20  
3.30  
3.40  
3.50  
Cycle-by-Cycle Operation  
During normal operation (when the output voltage is regulated),  
the voltage-error amplifier and the current comparator (CMPI)  
are the main control elements. (See the block diagram of Figure  
3.) During the on-time of the high side MOSFET, CMPI moni-  
tors the voltage between the SENSE+ and SENSE– pins. When  
the voltage level between the two pins reaches the threshold level  
VT1, the high side drive output is switched to ground, which  
turns off the high side MOSFET. The timing capacitor CT is  
then discharged at a rate determined by the off-time controller.  
While the timing capacitor is discharging, the low side drive  
output goes high, turning on the low side MOSFET. When the  
voltage level on the timing capacitor has discharged to the thresh-  
old voltage level VT2, comparator CMPT resets the SR flip-flop.  
The output of the flip-flop forces the low side drive output to go  
low and the high side drive output to go high. As a result, the low  
side switch is turned off and the high side switch is turned on.  
The sequence is then repeated. As the load current increases, the  
output voltage starts to decrease. This causes an increase in the  
output of the voltage-error amplifier, which, in turn, leads to an  
increase in the current comparator threshold VT1, thus tracking  
the load current. To prevent cross conduction of the external  
MOSFETs, feedback is incorporated to sense the state of the driver  
output pins. Before the low side drive output can go high, the  
high side drive output must be low. Likewise, the high side drive  
output is unable to go high while the low side drive output is high.  
Active Voltage Positioning  
The output voltage is sensed at the SENSE– pin. A voltage-  
error amplifier, (gm), amplifies the difference between the output  
voltage and a programmable reference voltage. The reference  
voltage is programmed to between 1.3 V and 3.5 V by an inter-  
nal 5-bit DAC, which reads the code at the voltage identifica-  
tion (VID) pins. (Refer to Table I for output voltage vs. VID pin  
code information.) A unique supplemental regulation technique  
called active voltage positioning with optimal compensation  
adjusts the output voltage as a function of the load current so  
that it is always optimally positioned for a load transient. Stan-  
dard (passive) voltage positioning, sometimes recommended for  
use with other architectures, has poor dynamic performance  
which renders it ineffective under the stringent repetitive tran-  
sient conditions specified in Intel VRM documents. Conse-  
quently, such techniques do not allow the minimum possible  
number of output capacitors to be used. Optimally compen-  
sated active voltage positioning as used in the ADP3155 pro-  
vides a bandwidth for transient response that is limited only by  
parasitic output inductance. This yields optimal load transient  
response with the minimum number of output capacitors.  
–6–  
REV. A  

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